1. Testing of Synchronous Sequential Circuits By Dr. Amin Danial Asham

2. References An Introduction to Logic Circuit Testing

3. A Model of Sequential Circuits Test generation for sequential circuits is extremely difficult because the behavior of a sequential circuit depends both on the present and on the past input values. The mathematical model of a synchronous sequential circuit is usually referred to as a sequential machine or a finite state machine (FSM). The following figure shows the general model of a synchronous sequential circuit. As can be seen from the diagram, sequential circuits are basically combinational circuits with memory to remember past inputs. primary (coming from the external environment)  The combinational part of the circuit receives two sets of input signals: and secondary (coming from the memory elements) The secondary input variables are also known as state variables. If there are m secondary input variables in a sequential circuit, then the circuit can be in any one of 2 m different present states

4. Testing of Synchronous Sequential Circuits Sequential circuits can be tested by checking that such a circuit functions as specified by its state table. This is an exhaustive approach and is practical only for small sequential circuits. Given the state table of a sequential circuit, find an input/output sequence pair (X,Z) such that the response of the circuit to X will be Z if and only if the circuit is operating correctly. The application of this input sequence X and the observation of the response, to see if it is Z, is called a checking experiment; the sequence pair (X, Z) is referred to as a checking sequence. The derivation of checking sequence for a sequential circuit is based on the following assumptions: The circuit is fully specified and deterministic. In a deterministic circuit the next state is determined uniquely by the present state and the present input. The circuit is strongly connected; that is, for every pair of states q i and q j of the circuit, there exists an input sequence that takes the circuit from q i to q j. The circuit in the presence of faults has no more states than those listed in its specification. In other words, the presence of a fault will not increase the number of states.

5. Definitions: 1.Homing Sequence (HS): An input sequence is said to be a homing sequence for a sequential circuit if the circuit’s response to the sequence is always sufficient to determine uniquely its final state. Example: New state Output Input Sequence: 10 1 D B C A C D B C C A B C

6. Definitions (cont.): 2.Distinguishing sequence (DS): A distinguishing sequence is an input sequence that, when applied to a sequential circuit, will produce a different output sequence for each choice of initial state.  Every distinguishing sequence is also a homing sequence because the knowledge of the initial state and the input sequence is always sufficient to determine uniquely the final state as well.  On the other hand, not every homing sequence is a distinguishing sequence. The output sequence that the machine produces in response to 101 uniquely specifies its initial state

7. Obtaining Homing and Distinguishing sequences If a Finite state machine with the following state table. We shall refer a collection of uncertainties, such as (B)(ACD) above, as an uncertainty vector (U). (B) and (ACD) in this example, are called the components of the uncertainty vector. For a component, the order of states is not important. Repetition of states are allowed and meaningful. Initially be in any of its four states; hence, the initial uncertainty is (ABCD) Consider the case that we just applied a 1 input, then the successor uncertainties will be (B) or (ACD), depending whether the output is 0 or 1, respectively. In this case: ( ) ( ) 0 ( ) 1 1 A D B A C B D C

8. Singleton: A component having a single state without duplication. Ex: (A), or (B). Note: (AA) is not a singleton. Homogeneous: A component having only one state, with or without duplications. Ex: (A), or (AA), or (BBB). Note: (AAB) is not homogeneous. Nonhomogeneous: A component containing at least two non-identical states. Ex: (AB) or (AAB) or (AAAC) or (AABC). Note: A component is either homogeneous or nonhomogeneous. Multiple: A component containing duplicate states. Ex: (AA) or (AAB) or (AAA) or (AABB) or (AABC). DEFINITONS (for components only)

9. DEFINITIONS (for vectors only) Trivial vector: All components are singletons. Ex: (A)(B)(C) or (A)(A)(B) or (C)(C)(C). Homogeneous vector: All components are homogeneous. Ex: (AA)(BBB)(C) or (AA)(B)(C) or (A)(B)(C) or (AA)(A)(B).

10. SUCCESSOR TREE Successor Tree: assuming we have a sequence machine with the following state table. (ABCD) (ABCD) 0 1 (AB) 0 (DD) 1 0 (BD) 0 (CC) 0 (AB) 0 (DD) 1 1 0 10 (A) 0 (D) 1 (DD) 1 (BC) 0 (AA) 0 1 0 (AB) 0 (DD) 0 (A) 0 (D) 1 (BB) 0 Loop Same Homing

11. Example Homing Sequence Distinguishing Sequence State Table Successor Tree 0 1 0 1 0 1 0 1 1 0 1 0 1 0 1 0 0 0 1 10 1 1 0 1 0 01 0 1 0 0 1 0 Init. State 00/01 Final state A Init. State 01/00 Final state B Init. State In/Out Final state Homing Distinguishing A 100/100 C B 100/101 A A or B as initial state with input sequence 00 produces 01 as output sequence.

12. Properties of the successor tree P1-Multiple component > multiple component. Ex. (BCC)(A) → (C)(AA)(C); (BCC)(A) → (BB)(A)(D) P2-Identical nonhomogeneous components > similar sub- trees [repeat]. Ex. (ABB), (AB), (AABB) are considered identical P3-Trivial vector: We have found a DS. Each state in the initial uncertainty vector responds to the input sequence leading to the trivial vector with a distinct output sequence. P4- Homogeneous vector: We have found a HS. The output sequence of the input sequence leading to the homogeneous vector allows us to uniquely determine the final state.

13. Homing Experiment Rule H1 [Repeat]: A node becomes terminal if the nonhomogeneous components are associated with some node in a preceding level (P2). Ex. (AB)(C)(D) is “identical” with (AAB)(B)(E)] Rule H2 [HS found]: All kth level nodes become terminal if any kth level node is associated with a homogeneous vector (P4) [only if we are seeking the shortest, or one of the shortest, HS].

14. Distinguishing Experiment Rule D1 [Repeat]: Identical to Rule H1. Rule D2 [Dead end]: A node becomes terminal if it is associated with a vector having a multiple component (P1). Rule D3 [DS found]: All kth level nodes become terminal if any kth level node is associated with a trivial vector (P3) [only if we are seeking the shortest, or one of the shortest, DS].

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