1. Execution Architecture MTT48 3 - 1 CPU08 Core M CPU08 INTRODUCTION

3. Execution Architecture MTT48 3 - 3 CPU08 Core M 68HC08 CPU System Integration Module (SIM) Clock Generation Module (CGM) Timer Interface Module (TIM) Direct Memory Access Module (DMA) Serial Communications Interface (SCI) Internal Bus (IBUS) Serial Peripheral Interface (SPI) Random Access Memory (RAM) Electronically Programmable Memory (EPROM) LVI COP Monitor ROM IRQ BREAK RESET CPU08

4. Execution Architecture MTT48 3 - 4 CPU08 Core M Module Exercise Objectives At end of sections coming up, will write Subroutine that clears all RAM locations Code sequence that executes at Power-on or RESET and calls the RAM clearing subroutine

5. Execution Architecture MTT48 3 - 5 CPU08 Core M CPU08 EXECUTION ARCHITECTURE

6. Execution Architecture MTT48 3 - 6 CPU08 Core M CPU08 Execution Architecture CPU08 is divided into two blocks Control unit –Contains a finite state machine, control and timing units that drive the execution unit Execution unit – Contains the ALU, registers, and bus interface

7. Execution Architecture MTT48 3 - 7 CPU08 Core M CPU08 Prefetch HC05 has many cycles where the address and data bus are idle CPU08 contains an opcode "look ahead" prefetch mechanism Performance increases were achieved by removing as many dead bus cycles as possible. CPU08 instruction flow was developed to be as efficient as possible in a pipelined architecture

8. Execution Architecture MTT48 3 - 8 CPU08 Core M Instruction Execution All instructions: Execute in a finite number of bus cycles –See individual instructions for number of bus cycles Load next opcode into Opcode Lookahead register Increment the Program Counter to next location –Happens after prefetch –Program Counter will be pointing to byte following prefetched opcode

9. Execution Architecture MTT48 3 - 9 CPU08 Core M Control Signals Two Control Unit signals control prefetch and instruction loading Opcode Lookahead –Signals prefetch operation Lastbox –Signals last cycle of current instruction

10. Execution Architecture MTT48 3 - 10 CPU08 Core M Programming Model Accumulator (A) Index Register (H:X) Stack Pointer (SP) Program Counter (PC) Condition Code Register (CCR)

11. Execution Architecture MTT48 3 - 11 CPU08 Core M Condition Code Registers Bits V - Two’s complement overflow flag Set if a signed arithmetic operation has overflowed Utilized in checking signed arithmetic operations H - Half Carry flag Set if a carry occurred from bit 3 to bit 4 Utilized in Binary Code Decimal (BCD) operations I - Global Interrupt Mask When set, disables CPU interrupts N - Negative Set if bit 7 is set in the Accumulator Z - Zero flag Set if all bits in the Accumulator are clear C - Carry or Borrow flag Set if a carry or borrow occurred during an operation

12. Execution Architecture MTT48 3 - 12 CPU08 Core M