1. EE 466/586 VLSI Design Partha Pande School of EECS Washington State University pande@eecs.wsu.edu

2. Lecture 26 SemiconductorMemories

3. Semiconductor Memory Classification Read-Write Memory Non-Volatile Read-Write Memory Read-Only Memory EPROM E 2 PROM FLASH Random Access Non-Random Access SRAM DRAM Mask-Programmed Programmable (PROM) FIFO Shift Register CAM LIFO

4. Memory Timing: Definitions

5. Memory Architecture: Decoders Word 0 Word 1 Word 2 WordN 2 2 N 2 1 Storage cell M bitsM N words S 0 S 1 S 2 S N 2 2 A 0 A 1 A K 2 1 K 5 log 2 N S N 2 1 Word 0 Word 1 Word 2 WordN 2 2 N 2 1 Storage cell S 0 Input-Output (M bits) Intuitive architecture for N x M memory Too many select signals: N words == N select signals K = log 2 N Decoder reduces the number of select signals Input-Output (M bits) Decoder

6. Array-Structured Memory Architecture Problem: ASPECT RATIO or HEIGHT >> WIDTH Amplify swing to rail-to-rail amplitude Selects appropriate word

7. Hierarchical Memory Architecture Advantages: 1. Shorter wires within blocks 2. Block address activates only 1 block => power savings

8. Row Decoders Collection of 2 M complex logic gates Organized in regular and dense fashion (N)AND Decoder NOR Decoder

9. Hierarchical Decoders A 2 A 2 A 2 A 3 WL 0 A 2 A 3 A 2 A 3 A 2 A 3 A 3 A 3 A 0 A 0 A 0 A 1 A 0 A 1 A 0 A 1 A 0 A 1 A 1 A 1 1 Multi-stage implementation improves performance NAND decoder using 2-input pre-decoders

10. Read-Write Memories (RAM)  STATIC (SRAM)  DYNAMIC (DRAM) Data stored as long as supply is applied Large (6 transistors/cell) Fast Differential Periodic refresh required Small (1-3 transistors/cell) Slower Single Ended

11. 6-transistor CMOS SRAM Cell WL b V DD M 3 M 4 M 6 M 1 M 5 M 2 b Q Q

12. Wordline and Bitline  Follow board notes

13. CMOS SRAM Analysis (Read) WL BL V DD M 3 M 4 M 6 M 1 V V V BL Q Q C bit C

14. Read Operation  Assume a “0” is stored on the left side of the cell, and a “1” on the right side.  M 1 is on and M 2 is off.  The row selection line is raised to V dd which turns on the access transistors  Current begins to flow through M 3 and M 1 to ground.  The resulting cell current slowly discharges the capacitance C bit.  On the other side of the cell, voltage on b remains high since there is no path to ground through M 2.  The difference between b and b is fed to a sense amplifier

15. Read Operation  Current flowing through M 3 and M 1 raises the output voltage at node q which could turn on M 2 and bring down the voltage at node q  It should not fall below V S  Size M 3 and M 1 appropriately.  Make conductance of M 1 3 to 4 times that of M 3 so that the drain voltage of M 1 does not rise above V TN  Cell discharge current  Follow board notes

16. CMOS SRAM Analysis (Read) 0 0 0.2 0.4 0.6 0.8 1 1.2 0.5 Voltage rise [V] 11.21.52 Cell Ratio (CR) 2.53 Voltage Rise (V)

17. CMOS SRAM Analysis (Write) BL = 1 = 0 Q Q M 1 M 6 M 3 M 4 V DD V WL

18. Write Operation  The operation of writing 0 or 1 is accomplished by forcing one bit line low while the other bit line remains at about V dd.  To write 1, b is forced low, and to write 0, b is forced low  Conditions for writing 1  Conductance of M 4 is several times larger than M 6 so that the drain of M 2 is pulled below V S.  M 1 turns off and its drain voltage rises to V DD due to the pull up action of M 5 and M 3.  M 2 turns on and assists M 4 in pulling output q to its intended low value.

19. Write Operation  Size transistor pair M 6 and M 4  When the cell is first turned on for the write operation, M 6 and M 4 form a pseudo-NMOS inverter.  Current flows through the two devices and lowers the voltage at node q from its starting value of V dd  The design of device sizes is based on pulling the node below V s

20. CMOS SRAM Analysis (Write)