1. THz Bipolar Transistor Circuits: Technical Feasibility, Technology Development, Integrated Circuit Results rodwell@ece.ucsb.edu 805-893-3244, 805-893-5705 fax Plenary, 2008 IEEE-CSIC Symposium, October 12, 2008 Mark Rodwell University of California, Santa Barbara Coauthors E. Lobisser, M. Wistey, V. Jain, A. Baraskar, J. Koo University of California, Santa Barbara E. Lind Lund University Z. Griffith, J. Hacker, M. Urteaga, D. Mensa, Richard Pierson, B. Brar Teledyne Scientific Company

2. The End is Near ( ! ) It's a great time to be working on electronics ! Things to work on: InP HEMTs & HBTs: extend (f , f max ) to 2-3 THz, build THz ICs The End (of Moore's Law) is Near (?) GaN HEMTs: develop V- and W-band power amplifiers Si MOSFETs: work to keep them scaling past 22 nm CMOS IC design: build ICs which bury the III-V's InGaAs MOSFETs: help keep VLSI scaling (maybe)

3. Scaling for THz Transistors

4. Simple Device Physics: Resistance Good approximation for contact widths less than 2 transfer lengths. bulk resistancecontact resistance -perpendicular contact resistance - parallel

5. Simple Device Physics: Depletion Layers capacitancetransit timespace-charge limited current

6. Simple Device Physics: Thermal Resistance Exact Carslaw & Jaeger 1959 Long, Narrow Stripe HBT Emitter, FET Gate Square ( L by L ) IC on heat sink

7. Simple Device Physics: Fringing Capacitance wiring capacitanceFET parasitic capacitances VLSI power-delay limits FET scaling constraints

8. Frequency Limits and Scaling Laws of (most) Electron Devices To double bandwidth, reduce thicknesses 2:1Improve contacts 4:1 reduce width 4:1, keep constant length increase current density 4:1 PIN photodiode

9. Bipolar Transistor Design

11. Bipolar Transistor Design: Scaling

12. parameterchange collector depletion layer thicknessdecrease 2:1 base thicknessdecrease 1.414:1 emitter junction widthdecrease 4:1 collector junction widthdecrease 4:1 emitter contact resistancedecrease 4:1 current densityincrease 4:1 base contact resistivitydecrease 4:1 Changes required to double transistor bandwidth: Linewidths scale as the inverse square of bandwidth because thermal constraints dominate. Bipolar Transistor Scaling Laws

13. Thermal Resistance Scaling : Transistor, Substrate, Package

14. Probable best solution: Thermal Vias ~500 nm below InP subcollector...over full active IC area.

15. InP Bipolar Transistor Scaling Roadmap emitter5122561286432 nm width 16 8421  m 2 access  base300 1751206030 nm contact width, 20 1052.51.25  m 2 contact  collector150 106755337.5 nm thick, 4.5 9183672 mA/  m 2 current density 4.9 43.32.752-2.5 V, breakdown f  370520 73010001400 GHz f max 490 850 130020002800 GHz power amplifiers 245 430 66010001400 GHz digital 2:1 divider 150 240 330480660 GHz industryuniversity →industry university 2007-8 appears feasible maybe

16. Can we make a 1 THz SiGe Bipolar Transistor ? InPSiGe emitter6418nm width 2 1.2  m 2 access  base6456nm contact width, 2.5 1.4  m 2 contact  collector53 15 nm thick 36125mA/  m 2 2.75 ??? V, breakdown f  10001000 GHz f max 20002000 GHz PAs10001000 GHz digital480480GHz (2:1 static divider metric) Assumes collector junction 3:1 wider than emitter. Assumes SiGe contacts 2:1 wider than junctions Simple physics clearly drives scaling transit times, C cb /I c → thinner layers, higher current density high power density → narrow junctions small junctions→ low resistance contacts Key challenge: Breakdown 15 nm collector → very low breakdown (also need better Ohmic contacts)

17. HBT Design For IC Performance from charge-control analysis:

18. InP HBT: Status

19. InP DHBTs: September 2008 250 nm 600nm 350 nm 250 nm 125 nm

20. 512 nm InP DHBT Production DDS IC: 4500 HBTs20-40 GHz op-amps 500 nm mesa HBT 150 GHz M/S latches175 GHz amplifiers Laboratory Technology Teledyne / BAETeledyne / UCSB UCSBUCSB / Teledyne / GCS 500 nm sidewall HBT f  = 405 GHz f max = 392 GHz V br, ceo = 4 V Teledyne 20 GHz clock 53-56 dBm OIP3 @ 2 GHz with 1 W dissipation ( Teledyne ) Z. Griffith M. Urteaga P. Rowell D. Pierson B. Brar V. Paidi

21. 256 nm Generation InP DHBT 150 nm thick collector 70 nm thick collector 60 nm thick collector 200 GHz master-slave latch design Z. Griffith, E. Lind J. Hacker, M. Jones 324 GHz Amplifier

22. 324 GHz Medium Power Amplifiers in 256 nm HBT ICs designed by Jon Hacker / Teledyne Teledyne 256 nm process flow- Hacker et al, 2008 IEEE MTT-S ~2 mW saturated output power

23. 128 / 64 / 32 nm HBT Technologies

24. Conventional ex-situ contacts are a mess textbook contact with surface oxide Interface barrier → resistance Further intermixing during high-current operation → degradation with metal penetration THz transistor bandwidths: very low-resistivity contacts are required

25. Improvements in Ohmic Contacts 128 nm generation requires ~ 4  - μm 2 emitter & base resistivities 64 nm generation requires ~ 2  - μm 2 Contacts to N-InGaAs*: Mo MBE in-situ 0.3 (+/- 0.7)  - μm 2 TiW ex-situ / NH4 pre-clean ~1 to 2  - μm 2 variable between process runs Contacts to P-InGaAs: Mo MBE in-situ below 2.5  - μm 2 Pd/Ti...ex-situ ~4  - μm 2 *measured emitter resistance remains higher than that of contacts.

26. Mo Emitter Contacts: Robust Integration into Process Flow Proposed Process Integration:

27. Process Must Change Greatly for 128 / 64 / 32 nm Nodes Undercutting of emitter ends control undercut → thinner emitter thinner emitter → thinner base metal thinner base metal → excess base metal resistance {101}A planes: fast {111}A planes: slow

28. 128 nm Emitter Process: Dry Etched Metal & Semiconductor Litho pattern metal sidewalldry etchwet etch results @ c.a. 200 nm emitter metal width Recent Results @ 128 nm emitter width to be submitted

29. Planarization E/B Processes for 64 & 32 nm Planarization boundary

30. What about InGaAs HEMTs ?...& InGaAs MOSFETS ?

31. InGaAs HEMTs and InGaAs MOSFETs high-K gate barrier N+ source/ drain by MBE regrowth SourceDrain Gate K Shinohara sub-22-nm InGaAs MOSFETs being developed for potential use in VLSI Efforts may: improve understanding HEMT & MOSFET scaling limits produce process modules which aid THz HEMTs Key III-V MOSFET scaling limits: low density of states→limits g m → C fringing /g m does not scale low m* → high well energy → minimum well thickness Additional HEMT scaling limits: high access resistance: barriers, recess regions, contacts limits to sheet concentration from small hetero-barrier energy

32. HBT Applications

33. Applications of THz InP HBTs Mixed-Signal ICs (ADCs, DACs, DDS) benefit in high-clock-rate ICs with 1k-3k devices lack of CMOS integration a major limitation → Mark Rosker's talk 600-1000 GHz transceiver ICs for low-volume military / scientific applications Precision GHz analog ICs using THz transistors → Sanjay Raman's talk, Zach Griffith's talks mm-Wave Power: 60 GHz & up GaN threatens, but f max → gain → PAE

34. Few-THz Bipolar Transistors Scaling limits: contact resistivities, device and IC thermal resistances. THz InP Bipolar Transistors: can it be done ? 62 nm (1 THz f , 1.5 THz f max ) scaling generation is feasible. 700 GHz amplifiers, 450 GHz digital logic Is the 32 nm (1 THz amplifiers) generation feasible ? THz InP Bipolar Transistors: what would we do with it ? Mixed-Signal IC Power density & CMOS integration are serious challenges Precision GHz analog systems mm-wave power Sub-mm-wave electronics