1. Cpu control.1 2/14 Datapath Components for Lab The Processor! (4.1- 4.4 4 th ed)

2. Cpu control.2 2/14 Functional Units Needed to build datapath

3. Cpu control.3 2/14 Review: How Registers work Register –Similar to D Flip Flop N-bit input and output Write Enable input –Write Enable: negated (0): Data Out will not change asserted (1): Data Out will become Data In after clock edge Clk Data In Write Enable NN Data Out

4. Cpu control.4 2/14 MIPS Register File Register File consists of 32 registers: –Two 32-bit output busses: Read data 1 & Read data 2 –A 32-bit input bus: write data Register is selected by: –R1 (read register 1) selects the register to put on read data 1 –R2 (read register 2) selects the register to put on read data 2 –RW (write register) selects the register to be written via (write data) when Write Enable is 1 (Regwrite) Clock input (CLK) –The CLK input is a factor ONLY during write operation –During read operation, behaves as a combinational logic block: Read data1 & read data 2 valid after “access time.” Clk Write data Write Enable 32 Read data 1 32 555 RWR1R2 32 32-bit Registers Read data 2

5. Cpu control.5 2/14 Memory Memory (Data) –input bus: Data In (Write data) –output bus: Data Out (Read Data) Memory word selected by: –Address selects word to put on Data Out –Write Enable = 1: address selects memory word to be written via the Data In bus (Memwrite) Clock input (CLK) (omitted from Book diag for simplicity) –The CLK input is a factor ONLY during write operation –During read operation, behaves as a combinational logic block: Address valid => Data Out valid after “access time.” Instruction memory data not shown in Book for simplicity Clk Data In Write Enable 32 DataOut Address read data Write data

6. Cpu control.6 2/14 Complete Single Cycle Datapath for : R, LD/ST, BEQ Can execute basic instructions in a single clock cycle No resource can be used more than one time during a single cycle

7. Cpu control.7 2/14 Datapath controlled by control unit

8. Cpu control.8 2/14 Requirements: CPU needs a 32-bit ALU (1) Functional Specification inputs: 2 x 32-bit operands A, B, 4-bit mode outputs:32-bit result S, 1-bit carry, 1 bit overflow operations:add, addu, sub, subu, and, or, xor, nor, slt, sltU (2) Block Diagram (schematic symbol/ Verilog description) ALU AB m ovf S 32 4 c

9. Cpu control.9 2/14 1-bit adder Review (Appendix B.5, B.6) ABCCoSum 00000 00101 01001 01110 10001 10110 11010 11111 Sum = a!bc! + ab!c! + a!b!c+abc = a b c = XOR Carryout = a!bc + ab!c + abc! + abc a b Sum Cin Co A B Cin sum 2 units of delay from A/B to sum 1unit of delay from Cin to sum

10. Cpu control.10 2/14 Carry Out circuit Cin a b Cout 2 units of delay from Cin to Cout

11. Cpu control.11 2/14 Additional operations: Subtract, AND, OR A - B = A + (– B) = A + B + 1 –form two complement by invert and add one A B 1-bit Full Adder CarryOut Mux CarryIn Result add and or S-select invert

12. Cpu control.12 2/14 1-bit ALU: AND, OR, a+b, a+b! Most significant bit ALU Delays Result = 1 gate delay From a to result = 2 Form b to Result = 2 (ignore b invert)

13. Cpu control.13 2/14 32-bit ALU using ripple carry adder Cin a0 b0 Sum0 Sum1 Sum2 Sum31 operation a1 b1 a31 b31 ALU0 ALU1 ALU2 ALU31

14. Cpu control.14 2/14 Final 32- bit ALU, including zero detect Operation