1. AKT211 – CAO 04 – x86 Architecture: Intel 8088 Ghifar Parahyangan Catholic University Sept 19, 2011 Ghifar Parahyangan Catholic University Sept 19, 2011

2. ReferenceReference Brey, Barry. “The Intel Microprocessor 8086/8088, 80186/80188, 80286, 80386, 80486, Pentium, and Pentium Pro Processor: Architecture, Programming, and Interfacing 4 th edition”. Prentice-Hall International Inc. 1997Brey, Barry. “The Intel Microprocessor 8086/8088, 80186/80188, 80286, 80386, 80486, Pentium, and Pentium Pro Processor: Architecture, Programming, and Interfacing 4 th edition”. Prentice-Hall International Inc. 1997

3. OutlineOutline  Intel x86 Architecture Evolution  The Programming Model  Register Types  Instruction Set  Data Types  Byte ordering  Memory Organization

4. Intel x86 Arch. Evolution 80808080 –The world’s 1 st general-purpose microprocessor –8-bit machine –8-bit data path to memory –Altair 80868086 –16-bit machine –wider data path, larger register –instruction cache / queue –1 st appearance of the x86 architecture –The variant : 8088, IBM’s 1 st personal computer –1-MByte memory addressing

5. Intel x86 Arch. Evolution 8028680286 –extension of 8086, enabled addressing a 16- MByte 8038680386 –Intel 1 st 32-bit machine –support multitasking 8048680486 –more sophisticated and powerful cache technology –sophisticated instruction pipelining –built-in math coprocessor

6. Intel x86 Arch. Evolution PentiumPentium –use of superscalar technology, allow multiple instructions to execute in parallel Pentium ProPentium Pro –aggressive use of register renaming –branch prediction, data flow analysis, speculative execution Pentium IIPentium II –Intel MMX technology, designed to process video, audio, and graphic data efficiently Pentium IIIPentium III –additional floating-point instructions to support 3D graphics software

7. Intel x86 Arch. Evolution Pentium 4Pentium 4 –Addition floating-point and other enhancements for multimed ia CoreCore –The 1 st Intel x86 microprocessor with a dual core: the implementation of two processor on a single chip Core 2Core 2 –extends to 64-bit –Core 2 Quad provides 4 processors on a single chip

8. The Programming Model of Intel

9. Register Types 1.General-purpose/multipurpose register  EAX, EBX, ECX, EDX, EBP, EDI, ESI 2.Special-purpose register  EIP, ESP, EFLAGS 3.Segment register  CS, DS, ES, SS, FS, GS

10. General-Purpose Register EAX (accumulator)EAX (accumulator) –32-bit register (EAX), as a 16-bit register (AX), or as either of two 8-bit registers (AH and AL) –used for instructions such as addition, subtraction, multiplication, division, and some of adjustment instructions –in 80386 above, it may also hold the offset address of a location in the memory system. EBX (base index)EBX (base index) –32-bit register (EBX), as a 16-bit register (BX), or as either of two 8-bit registers (BH and BL) –hold the offset address of a location in the memory system –in 80386 above, it also can address memory data

11. General-Purpose Register ECX (counter)ECX (counter) –hold the count for various instructions: repeated string instructions (REP/REPE/REPNE), shift, rotate, and LOOP/LOOPD –in 80386 above, it also can hold the offset address of memory data EDX (data)EDX (data) –holds a part of the result from a multiplication or part of the dividend before a division EBP (base pointer)EBP (base pointer) –points to a memory location for memory data transfer

12. General-Purpose Register EDI (destination index)EDI (destination index) –addresses string destination data for the string instructions ESI (source index)ESI (source index) –addresses source string data for the string instructions

13. Special-Purpose Register EIP (instruction pointer)EIP (instruction pointer) –addresses the next instruction in a section of memory defined as code segment –used to find the next sequential instruction in a program located within the code segment –can be modified with a jump or a call instruction ESP (stack pointer)ESP (stack pointer) –addresses an area of memory called stack –stack memory stores data through this pointer EFLAGSEFLAGS –indicate the condition of the microprocessor as well as control its operation

14. EFLAG and FLAG register (8086  Pentium)

15. EGLAG and FLAG register (8086  Pentium) C (carry)C (carry) –holds the carry after addition of the borrow after subtraction –also indicates error conditions as dictated by programs and procedures P (parity)P (parity) –a count of ones in a number expressed as even or odd –0: odd parity, 1: even parity –E.g.: If a number contains 3 binary one bits, it has odd parity. If a number contains zero one bits, it has even parity

16. EGLAG and FLAG register (8086  Pentium) A (auxiliary carry)A (auxiliary carry) –holds the carry (half-carry) after addition of the borrow after subtraction between bits position 3 and 4 of the result –used only by the DAA and DAS instructions to adjust the value of AL after a BCD addition or subtraction. Z (zero)Z (zero) –shows that the result of an arithmetic or logic operation is zero –1: zero, 0: not zero S (sign)S (sign) –holds the arithmetic sign of the result after execution –1: sign, 0: unsigned (positive)

17. EGLAG and FLAG register (8086  Pentium) T (trap)T (trap) –enables trapping through an on-chip debugging feature –1: interrupts the flow of the program –0: trapping/debugging feature is disabled I (interrupt)I (interrupt) –control the operation of the INTR (interrupt request) input pin D (direction)D (direction) –select either the increment or decrement mode for the DI and/or SI registers during string instruction

18. EGLAG and FLAG register (8086  Pentium) O (overflow)O (overflow) –indicates that the result has exceeded the capacity of the machine IOPL (I/O privilege level)IOPL (I/O privilege level) NT (nested task)NT (nested task) RF (resume)RF (resume) VM (virtual mode)VM (virtual mode) AC (alignment check)AC (alignment check) VIF (virtual interrupt flag)VIF (virtual interrupt flag) VIF (virtual interrupt pending)VIF (virtual interrupt pending) ID (identification)ID (identification)

19. Segment Register CS (code)CS (code) –holds the code (programs and procedures) used by microprocessor, defines the starting address of the section of memory holding code DS (data)DS (data) –contains most data used by a program –accessed by an offset address ES (extra)ES (extra) –used by some of the string instructions to hold destination data SS (stack)SS (stack) –defines the area of memory used for the stack FS & GS (stack)FS & GS (stack) –allow 2 additional memory segments for access by programs (80386 above)

20. Memory Organization

21. Instruction Set Data moving instructions.Data moving instructions. Arithmetic - add, subtract, increment, decrement, convert byte/word and compare.Arithmetic - add, subtract, increment, decrement, convert byte/word and compare. Logic - AND, OR, exclusive OR, shift/rotate and test.Logic - AND, OR, exclusive OR, shift/rotate and test. String manipulation - load, store, move, compare and scan for byte/word.String manipulation - load, store, move, compare and scan for byte/word. Control transfer - conditional, unconditional, call subroutine and return from subroutine.Control transfer - conditional, unconditional, call subroutine and return from subroutine. Input/Output instructions.Input/Output instructions. Other - setting/clearing flag bits, stack operations, software interrupts, etc.Other - setting/clearing flag bits, stack operations, software interrupts, etc.

22. Types of Operands AddressesAddresses NumbersNumbers –Integer/floating point CharactersCharacters –ASCII etc. Logical DataLogical Data –Bits or flags (Aside: Is there any difference between numbers and characters? Ask a C programmer!)(Aside: Is there any difference between numbers and characters? Ask a C programmer!)

23. Data Types in x86

24. General Data Types General Data Types 8 bit (Byte)8 bit (Byte) 16 bit (word)16 bit (word) 32 bit (double word)32 bit (double word) 64 bit (quad word)64 bit (quad word) 128 bit (double quadword)128 bit (double quadword) Addressing is by 8 bit unitAddressing is by 8 bit unit Words do not need to align at even- numbered addressWords do not need to align at even- numbered address Data accessed across 32 bit bus in units of double word read at addresses divisible by 4Data accessed across 32 bit bus in units of double word read at addresses divisible by 4 Little endianLittle endian

25. Numeric Data Types

26. Memory Organization generally consists of program, data, stackgenerally consists of program, data, stack their memories occupy the same memory spacetheir memories occupy the same memory space Total addressable memory size : 1 MBTotal addressable memory size : 1 MB

27. Byte Ordering What order do we read numbers that occupy more than one byte ?What order do we read numbers that occupy more than one byte ? e.g. (numbers in hex to make it easy to read)e.g. (numbers in hex to make it easy to read) –12345678 can be stored in 4x8bit locations as follows

28. Byte Ordering Big EndianBig Endian –Left  Right –Most significant byte in the lowest numerical byte address Little EndianLittle Endian –Right  Left –Least significant byte in the lowest numerical byte address

29. C Data Structure to Endian Mapping

30. Any Question ?

31. Assignment 2 Find the latest paper about research related to the recent processor technology and review itFind the latest paper about research related to the recent processor technology and review it Collect your review in hardcopy form at mid-semester testCollect your review in hardcopy form at mid-semester test

32. THANK YOU