1. Beam Secondary Shower Acquisition System: Front End: QIE10+GBTx+VTRx Student Meeting Jose Luis Sirvent PhD. Student 25/11/2013

2. QIE10 A GBTx Out [0:7] LVDS @ 80Mhz Reset SLVS @ 80Mhz CLK SLVS @ 40Mhz QIE10 B Reset SLVS @ 80Mhz CLK SLVS @ 40Mhz CMOS (3.3V) 5V (aVdd) 3.3V (dVdd) Gnd 1.5V (dVdd) 3.3V (Programming) VTRx 2.5V (VccRx=VccTx) TdRdI2C Switches Mode [0:3] Switches I2C Address [0:3] Connector I2C [0:3] 1. QIE10 Front-End detailed schematic: SRreset SRread DS90C032QML SRreset SRread SRin SRck DS90C032QML SRload SRin SRck DS90C032QML SRload DS90C031QML QIE10 SC-Write SLVS [0:9] 3.3V (dVdd) SRout QIE10 SC-Read LVDS [0:1] CImode Out [0:7] LVDS @ 80Mhz

3. 2. QIE10: Some considerations QIE10 Needs calibration through Serial Register! Serial Program Shift Register 64bits (CMOS 3.3V): SEU-Hard – LVDS/SLVS  Define input type for Clk (Default SLVD) – P0,P1  LVDS output level 150/250/350/450mV. – DiscOn  Enables the discriminator LVDS output (Default Off) – Tgain  Controls the timing amplifier gain. (Default Off) – Timming ThresholdDAC  8-bit threshold DAC for the timing circuit – TimingIref  3-bit code selecting an internal Rref resistance value – PedestalDAC  6-bit code controlling the pedestal DAC – CapCapID0pedestal  4-bit pedestal tweak for CapID0 – CapCapID1pedestal  4-bit pedestal tweak for CapID1 – CapCapID2pedestal  4-bit pedestal tweak for CapID2 – CapCapID3pedestal  4-bit pedestal tweak for CapID3 – FixRange  One bit to select the ranging mode. (Default 0 autorange) – RangeSet  2-bit code to set the range in fixed-range mode. – ChargeInjectDAC  3-bit code to set the magnitude of charge injection – Isetp  5-bit code to internally set the input amplifier bias level – Idcset  5-bit code to internally set the input splitter bias level (Idcset) – CALmode  Calibration mode select.

4. 3. Programming the QIE10 Register:

5. GBT Mode (Capabilities): – User Bandwidth: 3.36 Gb/s (80 bits each 25ns) Up to 40 bits @ 80Mhz (5 QIE10) Up to 20 bits @ 160Mhz Up to 10 bits @ 320Mhz – 32 bits Forward Error Correction (SEU protection) – External Control Field @80Mhz (Reset) 2 QIE10 Bandwidth Used = 40% 4. Optical transmission: Some considerations

6. 5. Standards LVDS channels have a low susceptibility to external noise because distant noise sources tend to add the same amount of voltage to both lines, so the difference between the voltages remains the same. The low common-mode voltage is the average of the voltages on the two traces—approximately 1.25V. The transmitter sets the common-mode voltage as an offset voltage from ground. The 350-mV differential voltage causes the LVDS to consume static power in the LVDS load resistor, depending on the 1.25V offset voltage and 350-mV differential-voltage swing. The JEDEC JESD8-13 SLVS-400 standard defines a point-to-point signaling method. SLVS uses smaller voltage swings and a lower common-mode voltage than LVDS. The 200-mV, or 400-mV-p-p, SLVS swing contributes to a reduction in power and is common in RSDS (reduced-swing-differential-signaling) standards. The RSDS standard reduces the swing from 350 mV to 200 mV with the same 1.25V common- mode offset of the LVDS standard. SLVS goes further and also reduces the common-mode voltage. The SLVS nominal common-mode voltage of 200 mV provides a considerable decrease in quiescent power. The combination of a smaller signal swing and low common-mode voltage produces much lower power consumption.

7. QIE10 A GBTx Out [0:7] LVDS @ 80Mhz Reset SLVS @ 80Mhz CLK SLVS @ 40Mhz QIE10 B Reset SLVS @ 80Mhz CLK SLVS @ 40Mhz CMOS (3.3V) VTRx 2.5V (VccRx=VccTx) TdRdI2C Switches Mode [0:3] Switches I2C Address [0:3] Connector I2C [0:3] SRreset SRread MAX9179 SRreset SRread SRin SRck MAX9179 SRload SRin SRck MAX9179 SRload MAX9112 QIE10 SC-Write SLVS [0:9] SRout QIE10 SC-Read LVDS [0:1] CImode Out [0:7] LVDS @ 80Mhz MAX9376 DC/DC 2.5V DC/DC 1.5V DC/DC 5V DC/DC 3.3V Power Supply 12V Switch 6. QIE10 Front-End detailed schematic:

8. 7. About Radiation: QIE10: 1KGy – http://www.physics.rutgers.edu/~tote/research/qie/hughes_1309_a0.pdf http://www.physics.rutgers.edu/~tote/research/qie/hughes_1309_a0.pdf GBTx: 1MGy – https://espace.cern.ch/GBT-Project/GBTX/Specifications/gbtxSpecsV1.8.pdf https://espace.cern.ch/GBT-Project/GBTX/Specifications/gbtxSpecsV1.8.pdf DS90C032QML (LVDS  CMOS): 1KGy – Texas Instruments “Commercially available”  Not in stock – http://www.ti.com/product/DS90C032QML-SP http://www.ti.com/product/DS90C032QML-SP DS90C031QML (CMOS  LVDS): 500Gy – Texas Instruments “Commercially available”  Not in stock – http://www.ti.com/product/DS90C031QML-SP http://www.ti.com/product/DS90C031QML-SP FEAST DC/DC Converters (>1MGy) – 10000 samples in 2014 – Vin<= 12V – Vout= 0.6-5V – Iout<= 4A – http://indico.cern.ch/getFile.py/access?contribId=14&sessionId=11&resId=0&materialId=slides&con fId=228972 http://indico.cern.ch/getFile.py/access?contribId=14&sessionId=11&resId=0&materialId=slides&con fId=228972

9. 8.Level Translators (Identiffied candidates) Level Translators FunctionalityReferenceCh.IC neededProviderVccSpeedTIDQualified by: SLVS  CMOS (GBTx  QIE10 Controls) MAX917943Maxim3.3V400Mbps-- DS90C032QML43TI3.3V<800Mbps1KGyProvider DS90LV048ATM43TI3.3V<800Mbps0.7kGy*ATLAS HXLVDSR43Honeywell3.3V100Mbps3KGyProvider SLVS  LVDS (GBTx  QIE10 Reset) MAX937621Maxim3.3V2Gbps-- UT54LVDM32881Aeroflex3.3V400Mbps3KGy**Provider CMOS  LVDS (QIE10 Controls  GBTx) MAX911221Maxim3.3V500Mbps-- DS90C031QML41TI3.3V<800Mbps1KGyProvider DS90LV047ATM41TI3.3V<400Mbps0.7KGy*ATLAS HXLVDSD41Honeywell3.3V100Mbps3KGyProvider UT54LVDM055LV21Aeroflex3.3V400Mbps3KGy**Provider *See super-nice Tullio Grassi’s list: https://twiki.cern.ch/twiki/bin/view/Main/TulliosPreferredPartList https://twiki.cern.ch/twiki/bin/view/Main/TulliosPreferredPartList **See LHCb COST rad Hard: http://lhcb-vd.web.cern.ch/lhcb-vd/ECS/http://lhcb-vd.web.cern.ch/lhcb-vd/ECS/ *** To be checked if we have our own CERN developments.

10. 9. Modules power supply (DC/DC) A very good candidate is the new CERN’s DC/DC module development based on “FEAST” ASIC Samples available: ~Q2_2014 Very flexible and compact modules Suited for 12V  0.6-5V

11. Quick comparison of dynamic ranges QIE10 has a pseudo-logaritmic scheme (this is not new) – Dynamic range equivalent to 17bits (1e5) – Constant Quantification error over the whole dynamics 10. Some more comparisons QIE VS ADC Digitalization schemes only

12. Gaussian wave digitalized with both schemes for direct comparison Quantification errors extracted and digitalization result shown and compared QIE10 is better in the tails but worse in average

13. Tests: o Chart A: Fitting error of different ADC & QIE10 versus Gaussian amplitude o Chart B: Fitting error of ADC versus number of bits Gaussian peak is the maximal count Statements: I.Under the best conditions a QIE10 encoded Gaussian is fitted with ~ 0.08% of error II.The QIE10 mean fitting error is equivalent to an ADC of 6.5 bits at full scale. III.For small signals (<5%) QIE10 performance is excellent compared to ADC’s IV.However QIE10 covers with 8 bits a huge dynamic range 1e5 (17 bits) Compromise:  Dynamic range VS Fitting error 10. Some more comparisons QIE VS ADC Digitalization schemes only

14. 11. Possibilities with ADC’s

15. From the GBTx bandwidth point of view: – Without FPGA’s or memory – Need of good synchronization (BST) Capabilities of GBTx as ADC driver OptionNumber of ADC’sBitsTotal InputsFsDynamics A21428 bits80 MSPS1e6 B31236 bits80 MSPS1e6 C21020 bits160 MSPS1e6 D11010 bits320 MSPS1e3 ShaperADC GBTx VTRxShaperADC Power 80MSPS (2 Points/Bunch) 160MSPS (4 Points/Bunch) 320MSPS (8 Points/Bunch)

16. 12. Digital Integration? If we set-up some specs: – 1e6 Dynamics – More than 10 Samples per 25ns  Fs > 400MSPS – Free-running  “Independent” Beam synchronous timing – Bunches re-construction and Dynamic Digital Integration Or Post-Mortem Data transmission – Rad-Hard components On-line transmission: – Running sums (window 10) need to be done in FPGA 400MhZ  40Mhz – FPGA Capabilities? FPGA Delay & Jitter? Post-Mortem transmission: – FPGA Stores raw data in memory to be latter transmitted to Back-End – No operations needed, but RH Memories?? – If 2x 12bits ADC 24 bits x sample, 10 samples bunch, 500Kbits per LHC turn, if minimum 3 points/sigma  ~9Mbits (1Mbyte) per scan. Reliable?? ShaperADC FPGAVTRxShaperADC Power Memory 400MSPS (10 Points/Bunch)

17. 12. Digital Integration? Some Numerical Analysis about this: – A) Impact of free-clock (400MSPS) in charge calculation – B) Impact of number of bits in charge calculation ADC Clock set at 400Mhz – Calculation of bunch integral (10 samples  25ns) – Clock phase changed (0  2π) – Number of bits changed (10  14) Results: – Charge Variation depending CLK phase  0.15% – Charge Resolution depending of Bits

18. 12. Digital Integration: Does the charge variation (due to CLK relative phase) depend on signal amplitude?

19. 12. Digital Integration: Does the charge variation (due to CLK relative phase) depend on signal amplitude? No, only the relative quantification error is decreasing when the signal is bigger. QIE10 Quantif error  ~ 1% ADC Digital Integration Quantif error  0.025% ADC Digital Integration phase error  0.15% ADC Digital Integration Incertitude  0.175%

20. 13. Signal with different beams (Fs=400MSPS)