1. Page Table Implementation

2. Readings r Silbershatz et al: 8.4-8.5

3. Outline r Translation Lookaside buffer (TLB) r Protection and Shared Pages r Dealing with Large Page Tables

4. TLB

5. Implementation of Page Table r The simplest approach is to have the page table implemented as a set of dedicated registers r Note: Not feasible to keep page table in registers m Why? Page tables can be very large m Context switching would be very expensive

6. Implementation of Page Table r Each process has a page table r Page table is kept in main memory r Page-table base register (PTBR) points to the page table r Page-table length register (PRLR) indicates size of the page table r Changing page tables requires changing only this one register during a contet switch

7. Implementation of Page Table r Problem: m Want to access location i m Two memory accesses: Index into the page table using the value in the PTBR offset by the location i. This gives the frame number Use the frame number to access the desired address r Solution: Use a special fast-lookup hardware cache called associative memory or translation look-aside buffers (TLBs)

8. TLB r Associative memory – parallel search r Address translation (p, d) m If p is in associative memory, get frame number out m Otherwise get frame number from page table in memory Page #Frame #

9. Paging Hardware With TLB

10. TLB r The TLB contains only a few of the page- table entries r When a logical address is generated by the CPU its page number is presented to the TLB. r If found the frame number is immediately available

11. TLB r If page number is not in TLB then a TLB miss occurs m The page table is consulted m The page number and frame number is added to the TLB m If the TLB is full then one of the entries is replaced m Example replacement policy: Least Recently Used (LRU) r A high hit rate has a high impact can dramatically reduce lookup time

12. Effective Access Time r TLB Lookup =  time unit r Memory cycle is 1 r Hit ratio =  m If hit the time to get page is 1 +  r Miss ratio = 1-  m If miss the time to get page is 2 +  r Effective Access Time (EAT) EAT = (1 +  )  + (2 +  )(1 –  ) = 2 +  – 

13. Effective Access Time r TLB Lookup = 20 nanoseconds r Hit ratio (percentage of times that a particular page is found in the TLB) = 80% r Time to access memory: 100 nanoseconds r TLB hit: m Time to get data: 120 r TLB miss: m Time to get data: 220 r Effective access time: m 0.80 * 120 + 0.2*220 = 140

14. Effective Access Time r Assume hit ratio is 98% (typical) r Effective access time: m 0.98 * 120 + 0.2*220 = 122

15. Protection and Shared Pages

16. Protection r Memory protection implemented by associating protection bit with each frame r One protection bit can define a page to be read-write or read-only

17. Shared Pages r Shared code m One copy of read-only (reentrant) code shared among processes (i.e., text editors, compilers, window systems). m Shared code must appear in same location in the logical address space of all processes r Private code and data m Each process keeps a separate copy of the code and data m The pages for the private code and data can appear anywhere in the logical address space

18. Shared Pages Example

19. Dealing with Large Page Tables

20. Structure of the Page Table r Typically systems have large logical address spaces r Page table could be excessively large r Example: m 32-bit logical address space The number of possible addresses in the logical address space is 2 32 m Page size is 4 KB (4096 bytes or 2 12 ) m Number of pages is 2 20 (20 bits for page number) m Page table may consist of up to 1 million entries r Take away message: Page table could be large

21. Structure of Page Table r Several approaches m MultiLevel Page tables m Hashed Page Tables m Inverted Page Tables

22. Two-Level Page-Table Scheme Page table is also paged Need to be able to index the outer page table

23. Two-Level Paging Example r A logical address (on 32-bit machine with 1K page size) is divided into: m A page number consisting of 22 bits m A page offset consisting of 10 bits r Since the page table is paged, the page number is further divided into: m A 12-bit page number m A 10-bit page offset

24. Two-Level Paging Example r Thus, a logical address is as follows: where p 1 is an index into the outer page table, and p 2 is the displacement within the page of the outer page table page numberpage offset p1p1 p2p2 d 12 10

25. Address-Translation Scheme r p 1 is used to index the outer page table r p 2 is used to index the page table

26. Multi-level Paging r What if you have a 64-bit architecture? r Do you think hierarchical paging is a good idea? m How many levels of paging are needed? m What is the relationship between paging and memory accesses? m 64-bit means that even the outer page is large The 64-bit UltraSPARC requires 7 levels of paging

27. Hashed Page Tables r Common in address spaces larger than 32 bits r The page number is hashed into a page table m This page table contains a chain of elements hashing to the same location r Virtual page numbers are compared in this chain searching for a match m If a match is found, the corresponding physical frame is extracted

28. Summary r This section studied implementation issues related to hash tables