1. Silicon Design Page 1 The Creation of a New Computer Chip

2. Silicon Design Page 2 A group of people from marketing, design, applications, manufacturing and finance develop the basic concept, features and rough specifications for a new product. Concept

3. Silicon Design Page 3 They all work on their particular pieces of the proposal Marketing –What are the customers asking for and what will sell vs. the competition, what is the marketing plan, what will it cost Design –How will it be designed, how long will it take, what design tools will be necessary, how many people will it take, what will it cost Manufacturing –How will it be manufactured, what tooling will be necessary, how many manufacturing lines will it need, what will it cost Finance –Will the product make money, what is the return on investment, what resources are available and what will need to be acquired, what will it cost

4. Silicon Design Page 4 They all get back together again with management and decide whether or not to proceed will the project. Decision

5. Silicon Design Page 5 GO! Once the decision is made to proceed, the design team swings into action!

6. Silicon Design Page 6 Logic Level RTL Level Transistor Level Logic Simulation Extract Parasitics & Create Timing Model RTL Simulation Block Level Physical Layout Level (Masks) The Design Flow

7. Silicon Design Page 7 The Block Diagram The problem is broken down into basic functional blocks and the interfaces are specified Memory RegistersALU Control Branch Control Clock & Timing I/O

8. Silicon Design Page 8 The High Level Description The main blocks are then broken down into smaller blocks. The functionality is coded in a high level descriptive language. This is known as the RTL description. operand selection and register control ALU controlmaster control IR Register File ALU

9. Silicon Design Page 9 High Level Simulation The RTL description is simulated to ensure that the design performs as it should.

10. Silicon Design Page 10 Logic Level Description The high-level RTL description is then converted to logic gates and registers. This is known as the logic level description.

11. Silicon Design Page 11 Logic Level Simulation The logic description is simulated to ensure that the design performs as it should. Results are compared against the RTL simulation.

12. Silicon Design Page 12 The Transistor Description The logic gates are broken down into their component transistors. From this description, timing delays and electrical parasitics can be estimated. If necessary, transistors can be resized. Field Effect Transistors N typeP type

13. Silicon Design Page 13 Field Effect Transistor Operation N type P type D S G S D G Gate = Ground = ‘0’ GND

14. Silicon Design Page 14 Field Effect Transistor Operation N type P type D S G S D G Gate = Vcc = ‘1’ VCC

15. Silicon Design Page 15 GND Anatomy of a N-Type Transistor Channel Length Via 45 nm available now (32 nm is next!) Si atom is about 0.1 nm Gate

16. Silicon Design Page 16 Anatomy of a N-Type Transistor Side View Top View Gate

17. Silicon Design Page 17 Silicon Wafer P-type Substrate GND Anatomy of a N-Type Transistor N-doped Silicon Silicon Dioxide (SiO 2 ) Metal Insulation/ Protection Polysilicon

18. Silicon Design Page 18 Silicon Wafer P-type Substrate GND N Type Field Effect Transistor no current flow

19. Silicon Design Page 19 Silicon Wafer P-type Substrate GND Vcc N Type Field Effect Transistor

20. Silicon Design Page 20 Silicon Wafer P-type Substrate GND Vcc N Type Field Effect Transistor

21. Silicon Design Page 21 Silicon Wafer P-type Substrate GND Vcc current flow N Type Field Effect Transistor

22. Silicon Design Page 22 Silicon Wafer P-type Substrate GND Vcc P Type Field Effect Transistor no current flow VccN-Well

23. Silicon Design Page 23 Silicon Wafer P-type Substrate GND P Type Field Effect Transistor VccN-Well

24. Silicon Design Page 24 Silicon Wafer P-type Substrate GND P Type Field Effect Transistor VccN-Well

25. Silicon Design Page 25 Silicon Wafer P-type Substrate GND P Type Field Effect Transistor VccN-Well current flow

26. Silicon Design Page 26 Logic Gate Implementation Using Field Effect Transistors P IO P P I1I2 O PP I1 O I2 O I1 I2 O IO

27. Silicon Design Page 27 Silicon Wafer P-type Substrate Silicon Wafer P-type Substrate So how do we build Field Effect Transistors? Process steps may vary. The process discussed here is representative, but leaves out many details. We start with a blank piece of silicon wafer

28. Silicon Design Page 28 Silicon Wafer P-type Substrate Silicon Wafer P-type Substrate Cover it with an N-well Mask Silicon Wafer P-type Substrate Silicon Wafer P-type Substrate The technique used to selectively mask regions of the chip is called photolithography.

29. Silicon Design Page 29 N-type dopant Silicon Wafer P-type Substrate Silicon Wafer P-type Substrate Silicon Wafer P-type Substrate Silicon Wafer P-type Substrate Dope regions of the substrate using diffusion or ion implantation to create the N-well

30. Silicon Design Page 30 N-type dopant Silicon Wafer P-type Substrate Silicon Wafer P-type Substrate Silicon Wafer P-type Substrate Silicon Wafer P-type Substrate Dope regions of the substrate using diffusion or ion implantation to create the N-well

31. Silicon Design Page 31 N-type dopant Silicon Wafer P-type Substrate Silicon Wafer P-type Substrate Silicon Wafer P-type Substrate Silicon Wafer P-type Substrate N-Well Dope regions of the substrate using diffusion or ion implantation to create the N-well

32. Silicon Design Page 32 Silicon Wafer P-type Substrate Silicon Wafer P-type Substrate Silicon Wafer P-type Substrate Silicon Wafer P-type Substrate N-Well Mask is Removed

33. Silicon Design Page 33 Silicon Wafer P-type Substrate Silicon Wafer P-type Substrate Silicon Wafer P-type Substrate Silicon Wafer P-type Substrate Grow the Gate Oxide Layer (SiO 2 )

34. Silicon Design Page 34 Silicon Wafer P-type Substrate Silicon Wafer P-type Substrate Silicon Wafer P-type Substrate Silicon Wafer P-type Substrate Deposit Polysilicon (a.k.a. Polycrystaline Silicon, or “poly”)

35. Silicon Design Page 35 Silicon Wafer P-type Substrate Silicon Wafer P-type Substrate Silicon Wafer P-type Substrate Silicon Wafer P-type Substrate Deposit Polysilicon (a.k.a. Polycrystaline Silicon, or “poly”) Polysilicon

36. Silicon Design Page 36 Cover it with a Polysilicon mask Silicon Wafer P-type Substrate Silicon Wafer P-type Substrate Silicon Wafer P-type Substrate Silicon Wafer P-type Substrate

37. Silicon Design Page 37 Etchant Etch the Polysilicon and Oxide Silicon Wafer P-type Substrate Silicon Wafer P-type Substrate Silicon Wafer P-type Substrate Silicon Wafer P-type Substrate

38. Silicon Design Page 38 Etchant Silicon Wafer P-type Substrate Silicon Wafer P-type Substrate Silicon Wafer P-type Substrate Silicon Wafer P-type Substrate Etch the Polysilicon and Oxide

39. Silicon Design Page 39 Etchant Silicon Wafer P-type Substrate Silicon Wafer P-type Substrate Silicon Wafer P-type Substrate Silicon Wafer P-type Substrate Etch the Polysilicon and Oxide

40. Silicon Design Page 40 Silicon Wafer P-type Substrate Silicon Wafer P-type Substrate Silicon Wafer P-type Substrate Silicon Wafer P-type Substrate Etch the Polysilicon and Oxide

41. Silicon Design Page 41 Cover it with an N transistor mask Silicon Wafer P-type Substrate Silicon Wafer P-type Substrate Silicon Wafer P-type Substrate Silicon Wafer P-type Substrate

42. Silicon Design Page 42 Implant N type dopant Silicon Wafer P-type Substrate Silicon Wafer P-type Substrate Silicon Wafer P-type Substrate Silicon Wafer P-type Substrate N-type dopant

43. Silicon Design Page 43 Implant N type dopant Silicon Wafer P-type Substrate Silicon Wafer P-type Substrate Silicon Wafer P-type Substrate Silicon Wafer P-type Substrate N-type dopant

44. Silicon Design Page 44 Cover it with a P Transistor mask Silicon Wafer P-type Substrate Silicon Wafer P-type Substrate Silicon Wafer P-type Substrate Silicon Wafer P-type Substrate

45. Silicon Design Page 45 Implant P Dopant Silicon Wafer P-type Substrate Silicon Wafer P-type Substrate Silicon Wafer P-type Substrate Silicon Wafer P-type Substrate P-type dopant

46. Silicon Design Page 46 Implant P Dopant Silicon Wafer P-type Substrate Silicon Wafer P-type Substrate Silicon Wafer P-type Substrate Silicon Wafer P-type Substrate P-type dopant

47. Silicon Design Page 47 Silicon Wafer P-type Substrate Silicon Wafer P-type Substrate Silicon Wafer P-type Substrate Silicon Wafer P-type Substrate Grow more Oxide

48. Silicon Design Page 48 Silicon Wafer P-type Substrate Silicon Wafer P-type Substrate Silicon Wafer P-type Substrate Silicon Wafer P-type Substrate Grow more Oxide SiO 2

49. Silicon Design Page 49 Cover it with a Contact mask Silicon Wafer P-type Substrate Silicon Wafer P-type Substrate Silicon Wafer P-type Substrate Silicon Wafer P-type Substrate

50. Silicon Design Page 50 Etch the Oxide Silicon Wafer P-type Substrate Silicon Wafer P-type Substrate Silicon Wafer P-type Substrate Silicon Wafer P-type Substrate Etchant

51. Silicon Design Page 51 Silicon Wafer P-type Substrate Silicon Wafer P-type Substrate Silicon Wafer P-type Substrate Silicon Wafer P-type Substrate Etchant Etch the Oxide

52. Silicon Design Page 52 Deposit Metal Silicon Wafer P-type Substrate Silicon Wafer P-type Substrate Silicon Wafer P-type Substrate Silicon Wafer P-type Substrate

53. Silicon Design Page 53 Deposit Metal Silicon Wafer P-type Substrate Silicon Wafer P-type Substrate Silicon Wafer P-type Substrate Silicon Wafer P-type Substrate Vias

54. Silicon Design Page 54 Cover it with a Metal mask Silicon Wafer P-type Substrate Silicon Wafer P-type Substrate Silicon Wafer P-type Substrate Silicon Wafer P-type Substrate

55. Silicon Design Page 55 Etch the Metal Silicon Wafer P-type Substrate Silicon Wafer P-type Substrate Silicon Wafer P-type Substrate Silicon Wafer P-type Substrate Etchant

56. Silicon Design Page 56 Etch the Metal Silicon Wafer P-type Substrate Silicon Wafer P-type Substrate Silicon Wafer P-type Substrate Silicon Wafer P-type Substrate Etchant

57. Silicon Design Page 57 Deposit Insulation Silicon Wafer P-type Substrate Silicon Wafer P-type Substrate Silicon Wafer P-type Substrate Silicon Wafer P-type Substrate

58. Silicon Design Page 58 Deposit Insulation Silicon Wafer P-type Substrate Silicon Wafer P-type Substrate Silicon Wafer P-type Substrate Silicon Wafer P-type Substrate

59. Silicon Design Page 59 Repeat for additional metal layers Silicon Wafer P-type Substrate Silicon Wafer P-type Substrate Silicon Wafer P-type Substrate Silicon Wafer P-type Substrate

60. Silicon Design Page 60 A CMOS Inverter IN OUT Gnd Vcc N-well P IO IO

61. Silicon Design Page 61 N-well Mask

62. Silicon Design Page 62 Polysilicon Mask

63. Silicon Design Page 63 N Transistor Mask

64. Silicon Design Page 64 P Transistor Mask

65. Silicon Design Page 65 Metal Mask

66. Silicon Design Page 66 Contact Mask

67. Silicon Design Page 67 IN OUT Gnd Vcc N-well The Completed Circuit

68. Silicon Design Page 68 Partial Die Plots

69. Silicon Design Page 69 More Partial Die Plots

70. Silicon Design Page 70 Complete Chip Plot Intel Microcontroller Chip – 80C196KJ

71. Silicon Design Page 71 Intel Pentium 4

72. Silicon Design Page 72 Intel Core 2 Duo

73. Silicon Design Page 73 Processed Silicon Wafer A wafer A die

74. Silicon Design Page 74 Wafer Fabrication Preceding steps done in a “fab” –Silicon wafer fabrication facility Fabs are expensive –Rely on high volumes to get part cost down

75. Silicon Design Page 75 Post-Wafer Fabrication Each die is tested to see which work Wafer is cut up –Bad dies are thrown away –Good dies are kept and packaged

76. Silicon Design Page 76 Packaging Various package types exist. Each may require different packaging techniques.

77. Silicon Design Page 77 Wire Bond Packaging

78. Silicon Design Page 78 Wire Bond Packaging

79. Silicon Design Page 79 Wire Bond

80. Silicon Design Page 80 Wire Bond vs. Flip Chip Packaging

81. Silicon Design Page 81 Final Testing Packaged chips are tested again –Burn-in used to eliminate infant mortality Good chips labeled and shipped