Presentation is loading. Please wait.

Presentation is loading. Please wait.

DØ Silicon Microstrip Tracker for runIIa Eric Kajfasz (CPPMarseille) Vertex2002 - Hawaii, November 4, 2002 Design Production Assembly Readout Installation.

Similar presentations


Presentation on theme: "DØ Silicon Microstrip Tracker for runIIa Eric Kajfasz (CPPMarseille) Vertex2002 - Hawaii, November 4, 2002 Design Production Assembly Readout Installation."— Presentation transcript:

1 DØ Silicon Microstrip Tracker for runIIa Eric Kajfasz (CPPMarseille) Vertex2002 - Hawaii, November 4, 2002 Design Production Assembly Readout Installation Commissioning/Operation Some results DØSMT

2 Vertex2002, 11/05/02E. Kajfasz2 Fermilab Tevatron Main Injector & Recycler Tevatron Chicago   p source Booster pp p p pp 1.96 TeV CDF DØ Run 1  Run 2A  Run 2B 0.1 fb -1  2 fb -1  15 fb -1 4.82.32.5 interactions/xing 1323963500 bunch xing (ns) 10517.33.2  Ldt (pb -1 /week) 5.2x10 32 8.6x10 31 1.6x10 30 typ L (cm -2 s -1 ) 1.96 1.8  s (TeV) 140x10336x366x6 #bunches Run 2BRun 2ARun 1B Tevatron upgrade

3 Vertex2002, 11/05/02E. Kajfasz3 The DØ Detector Calorimeters Tracker Muon System Beamline Shielding Electronics protons 20 m

4 Vertex2002, 11/05/02E. Kajfasz4 RunIIa SMT Design (2T)

5 Vertex2002, 11/05/02E. Kajfasz5 SVXIIe chip 1.2 um CMOS amplifier/analog delay/ADC chip fabricated in the UTMC rad hard process Designed by LBL/FNAL Some features: 128 channels 32 cell pipeline/channel 8-bit Wilkinson ADCs Sparsification 53 MHz readout 106 MHz digitization 6.4 x 9.7 mm2 ~ 85,000 transistors noise: 490e + 50e/pF Pipeline Control Logic Analog Pipeline 128 channels 32 storage cells/channel Integrators (128 channels) ADC Comparators Sparsification FIFO I/O ADC ramp and counter SVXIIFESVXIIBE Analog sectionDigital section To Silicon Detector To Readout System

6 Vertex2002, 11/05/02E. Kajfasz6 High Density Interconnect Kapton based flex circuits with 0.2 mm pitch for chip mounting Laminated to Beryllium substrate and glued to Silicon sensor Connects Sensor to SVXII chips and SVXII chips to flex circuit via wire bonds (Al wedge bonding) Connects to a Low Mass Cable which carries the signals out of the interaction region Be substrate SVXIIE chips 9-chip HDI for 2 0 sensor Bus control and power traces

7 Vertex2002, 11/05/02E. Kajfasz7 Production: ladder design Be substrate wire bonds Silicon support rails Be support (Bulkhead) including cooling channel vertical scale

8 Vertex2002, 11/05/02E. Kajfasz8 Family of D0SMT Detector types (all AC coupled) L3 L6 L9 F6 F8 H6 n-side p-side 144 DSDM 72 Single Sided 50 um pitch 216 DS 2 o stereo 144 DS +/- 15 o stereo 50 (p)/153(n) um 50 (p)/60(n) um 50 (p)/62.5(n) um 92x2 SS +/- 7.5 o Elma-Russia 70% Micron-UK, 30% Eurysis-France Micron-UK

9 Vertex2002, 11/05/02E. Kajfasz9 RunIIa SMT Design 6 Barrels 12 F-Disks 4 H-Disks 6192 R/O chips = 792,576 channels > 1.5 million wire bonds 8 layers 72 ladders 12 cm long Layers 1,2,5,6: L3 or L6 Layers 3,4,7,8: L9 Barrel F-Disk H-Disk 12 F-wedges 24 H-wedges North South 1/2-cylinder

10 Vertex2002, 11/05/02E. Kajfasz10 Production: Rates Production mainly paced by problems with HDIs and Silicon sensors (yields, delivery delays …)

11 Vertex2002, 11/05/02E. Kajfasz11 Production: Sensor problems Sensor lithography defects A silicon manufacturing problem produced p-stop isolation defects in the 90° stereo ladders. This resulted in a 30% yield from the manufacturer. Micro-discharge effect With negative p-side bias on double-sided detectors, we observed micro-discharges producing large leakage currents and noise above a certain breakdown voltage. The effect occurs along the edges of the p implants, where large field distortions and charge accumulations result from misalignment of electrodes with implants.

12 Vertex2002, 11/05/02E. Kajfasz12 Production: V-max L6L9 FW |V-max| (V)

13 Vertex2002, 11/05/02E. Kajfasz13 Assembly: Barrel assembly Ladders placed on barrels using an insertion fixture Internal alignment done using a CMM (touch probe)

14 Vertex2002, 11/05/02E. Kajfasz14 Assembly: Barrel 2 alignment  Active BH Passive BH    In the plane of the ladder Around ladder short axisAround ladder long axis   (mm) 10um 48um =10um induces a 3um error  =48um induces a 3um error=48um induces a 2um error  

15 Vertex2002, 11/05/02E. Kajfasz15 Assembly: Barrel-Fdisk mating

16 Vertex2002, 11/05/02E. Kajfasz16 Assembly: End Fdisks mating

17 Vertex2002, 11/05/02E. Kajfasz17 Assembly: Hdisk

18 Vertex2002, 11/05/02E. Kajfasz18 Assembly: Radiation monitors

19 Vertex2002, 11/05/02E. Kajfasz19 Assembly: 1/2-cylinder HDI connection to low-mass cable South Half Cylinder

20 Vertex2002, 11/05/02E. Kajfasz20 ~19’-30’ High Mass Cable (3M/80 conductor) Serial Command Link Cathedral Interface Board Crates (8x18) 8’ Low Mass Cables 3/6/8/9 Chip HDI Sensor CLKs Horse Shoe 3/6/8/9 Chip HDI Sensor Adaptor card 25’ High Mass Cable (3M/50 conductor) CLKs IBIB MCH2 VRBCVRBC SBCSBC VRBVRB Pwr PC Monitoring SDAQ PDAQ (L3) VRB Crates (12x10) Platform SEQSEQ SEQ Controller Optical Link 1Gb/s Sequencer Crates (6x20) VTM Around Iteraction Region CLKs MCH3 Pwr PC 15531553 PowerPCs and Single Board Computers are accessed thru Ethernet MCH2 Pwr PC HVmodHVmod HV Crates (8x6+2x4) Cathedral Fuse Panel Bulk LV Power Supplies HV fanout 1=>4 HV breakout box VME Crates (4x3) 25 twisted pair cables 17 twisted pair cables HV LV I,V,T Monitoring

21 Vertex2002, 11/05/02E. Kajfasz21 Readout Electronics Interface Boards 8 crates (144 boards) located inside the detector volume Regenerates signals SVX monitoring and power management Bias voltage distribution SEQuencers 6 crates (120 boards) located on the detector platform Use SVX control lines to actuate acquisition, digitization and readout Convert SVX data to optical signals VRBs (Readout Buffers) 12 crates (120 boards) located in counting house Data buffer pending L2 trigger decision Input @ 5-10 kHz L1 accept rate ~ 50 Mb/s/channel Output @ 1 kHz L2 accept rate ~ 50 Mb/s

22 Vertex2002, 11/05/02E. Kajfasz22 HV distribution HV Modules (MCH2) Fanout Boxes (MCH2) Breakout Boxes (Platform)

23 Vertex2002, 11/05/02E. Kajfasz23 B5 B4 B6 B2 B3 B1 SW1 SW0NW0 NW1 SW1 SE NWNE SW INTERFACE BOARD CRATES ADAPTER CARDS 80/3M CABLE L.M. CABLE SE0 120 ladders 72 F-wedges 48 H-wedges SE1 SW0 H2 H1 H4 H3 Central Calo CFT F6 F5 F4 F3 F2 F1 F12 F11 F10 F9 F8 F7 Calo North End Cap Calo South End Cap Muon wall East Cathedral West Cathedral

24 Vertex2002, 11/05/02E. Kajfasz24 Installation Cylinder installation was completed on 12/20/00 A 1/2-cylinder of 3 barrels and 6 F disks was inserted into each end of the CFT bore H Disk installation was completed on 2/6/01 The cabling (~15,000 connections) and electronics installation was completed in May 2001 Fiber Tracker Low Mass Cables High Mass Cables SMT Interface Boards Calorimeter

25 Vertex2002, 11/05/02E. Kajfasz25 Installation: Cooling system 30% glycol + water at –10 o C (=> detectors between –5 and 0 o C) The tracking volume is purged with dry air to prevent condensation

26 Vertex2002, 11/05/02E. Kajfasz26 Commissioning: Status entire detector is connected and powered currently collecting essentially physics data. Calibration and commissioning data when no beam present some problems we run into: had failure of some IB LV PS. Fixed and reliable now. IB crate heat exchangers water leak => had to disconnect 2 out of 8 Hygroscopicity and not-too-professional assembly of some HV fan out boxes leading to bias current instabilities => tried to fix them but designed and ordered new ones Failure of a few detectors since the last shutdown => not necessarily an HDI problem. Part of them will be fixed in January 2003. Fraction of enabled detectors: on 12/01/01: 93% (Barrels) - 95% (F-Disks) - 90% (H-Disks) on 09/31/02: 89% (Barrels) - 94% (F-Disks) - 84% (H-Disks)

27 Vertex2002, 11/05/02E. Kajfasz27 Commissioning: Charge collection Cluster charge (corrected for track angle): 1 mip ~ 25 ADC counts. Noise < 2ADC counts. p-side pulse-height (ADC) n-side pulse-height (ADC) Charge correlation between p- and n-side of a detector p-side pulse-height (ADC) Lorentz angle: The charge deflection due to the magnetic field fraction of 1 strip clusters Local track incidence angle  L =4.5°

28 Vertex2002, 11/05/02E. Kajfasz28 Operations: Calibrations SMT pedestal, noise and gain measurements are taken using SDAQ. Pedestal and noise measurements are used to calculate the threshold per chip to be used in sparse read out

29 Vertex2002, 11/05/02E. Kajfasz29 Operations issues a quiet event

30 Vertex2002, 11/05/02E. Kajfasz30 Operations issues a busy event

31 Vertex2002, 11/05/02E. Kajfasz31 Operations issues: Pedestal shifts 3 superbunches of 12 bunches tick number pedestals seem to be different at the beginning of each superbunch Investigating...

32 Vertex2002, 11/05/02E. Kajfasz32 Operations issues: F-Wedges noise (1) F11-1-2 seems to affect only the p-side of a fraction of the Micron sensors does not seem to depend on the biasing scheme does not seem to depend on temperature still investigating...

33 Vertex2002, 11/05/02E. Kajfasz33 Operation issues: F-Wedges noise (2) # of wedges in disk w/ > 10% noisy stripsw/ > 20% noisy stripsw/ > 30% noisy strips P-sideN-sideP-sideN-sideP-sideN-side threshold (ADC)4610446 446 4 01 (Micron)641322111100 02 (Micron)410120011001 03 (Eurysis)000000000000 04 (Micron)542243113211 05 (Eurysis)000100010000 06 (Micron)755765344324 07 (Micron)322122101100 08 (Eurysis)000000000000 09 (Micron)443243112201 10 (Eurysis)000000000000 11 (Micron)533432012100 12 (Micron)632222202200 TOTAL (144)402618232519910161237

34 Vertex2002, 11/05/02E. Kajfasz34 Bias currents: first look (1) wi(l)de range of behavior... current (uA) this is not bulk current.

35 Vertex2002, 11/05/02E. Kajfasz35 Bias currents: first look (2) current (uA) 2Ly5+2Ly6 1Ly3+2Ly4 2Ly7+2Ly8 2Ly1+1Ly2 4Ly1 2Ly1+1Ly2 As expected, the closer you get from the beam and the fastest the bulk current increases with time (i.e. integrated luminosity)

36 Vertex2002, 11/05/02E. Kajfasz36 Bias currents: first look (3) Roughly scales with luminosity back of the envelop calculation: 1uA/20pb -1 => 100uA/2fb -1 Very preliminary. Need to have a closer look. current (uA) Integrated Luminosity (pb-1) bias current inner layer Integrated Luminosity Days since 03/01/2001

37 Vertex2002, 11/05/02E. Kajfasz37 Expected depletion voltage

38 Vertex2002, 11/05/02E. Kajfasz38 Results: Tracking and Vertexing (prelim.) DCA track x y Impact parameter resolution SMT track CFT track CFT-SMT track matching Vertex measurements

39 Vertex2002, 11/05/02E. Kajfasz39 Results: b-tagging (preliminary) Preliminary results indicate b-tagging efficiency as high as 60% can be achieved Mis-tagging rate for c- jets is less than 15 - 20% depending on E T, while light quark rate can be kept at a few percent level Tagging in  +jet data sample: muon p T rel > 1.5 GeV wrt the jet D  Run 2 Preliminary

40 Vertex2002, 11/05/02E. Kajfasz40 B-physics (preliminary) Proper B decay length (B  J/  +X) Data Background from sidebands Backgrounds from prompt J/  B-lifetime signal Signal + background mass (  +  - K ± ) B ±  J/  K ± First time in DØ !

41 Vertex2002, 11/05/02E. Kajfasz41 Physics with tracking (preliminary) J/  e + e - Muon System Calorimeter J/  and  ’ W  e E(cluster)/p(track) Combine tracking with other systems Z  +  - ~170 evts

42 Vertex2002, 11/05/02E. Kajfasz42 Conclusions Design/Production Experience with double-sided detectors has led to the decision to use single-sided silicon for the upgrade. Should work towards simpler designs in the future. For example, using 6 different sensor types resulted in extensive logistical complications. Had to overcome numerous vendor related problems for HDIs, Silicon Sensors, jumpers, low mass cables … Assembly/Installation First alignment results show that the DØ SMT was assembled and installed very well. The installation in the D0 detector went rather smoothly. The biggest challenge to overcome was the lack of real estate. The D0 detector, when first designed, was unfortunately not designed with a Silicon detector in mind

43 Vertex2002, 11/05/02E. Kajfasz43 Conclusions Commissioning and operation The SMT was the first major DØ Upgrade detector system fully operational for Run 2a. We had our share of mishaps (IB PS, IB crate water leak,...), but recovered from them. 90% of the channels are functional, and most of the remaining channels will be debugged and should hopefully be recovered during the January 2003 shutdown. Calibrations and first look at physics show that we understand our detector. Altough the detector is close to being fully commissioned, some studies still need to be completed.

44 Vertex2002, 11/05/02E. Kajfasz44 Partial to-do list Some studies to complete: Pedestal shifts where does it come from how to suppress it F-wedge excess noise: where does it come from how to suppress it Bias currents: study the effect of radiation Effect of magnetic field on wire bonds Go to the next level of sophistication: Online: develop more monitoring tools Offline: alignment clustering tracking (efficiency, fully implement disks...) simulation

45 Vertex2002, 11/05/02E. Kajfasz45 Conclusions General Construction and commissioning of the SMT has been an adventure full of challenges. But thanks to the relentless efforts of many physicists, engineers and technicians, D0 has now a vertex detector to do physics with. Results start pouring... We had so much fun building this detector for run 2a that we are planning to build a completely new Silicon Microstrip detector for run 2b (see Kazu’s talk)


Download ppt "DØ Silicon Microstrip Tracker for runIIa Eric Kajfasz (CPPMarseille) Vertex2002 - Hawaii, November 4, 2002 Design Production Assembly Readout Installation."

Similar presentations


Ads by Google