1. Class Report 何昭毅 : Voltage Scaling

2. Source of CMOS Power Consumption  Dynamic power consumption  Short circuit power consumption  Leakage power consumption

3. CMOS Power and Delay  CMOS circuit design is to reduce the values of , C L, V DD, and f by applying all possible techniques at all levels of the VLSI system without sacrificing T D.  T D is set to be the critical path time delay Set V t = 0.6

4. Voltage Scaling Changing a processor clock frequency does not reduce the energy required to perform a given task. Lowering the voltage actually reduces the energy required to perform a fixed amount of work. Simplified properties of voltage scaling Energy  V 2 & Speed  V  Energy  Speed !!! Trading voltage for performance can be a huge win. !!!

5. Dynamic Voltage Scaling  Time-slicing (TDM) technique will be applied to DVB-Mobile application. The desired data will be received in higher speed but short interval.  Assume the data is received 1ms in every 6ms. Time Voltage 1ms3ms6ms Power ConsumptionHigh Median Low

6. Voltage Scaling - Pipelined  Reference Architecture: V DD f A  Pipelined Architecture: V DD /N f A1A1 A1A1 A1A1 ff CLCL C L /M

7. Pipelined Architecture - Example f f f Comparator A>B A B C f f f Comparator A>B A B C f f

8. Voltage Scaling - Parallel  Reference Architecture: V DD f A CLCL  Parallel Architecture: V DD /N A1A1 CLCL A2A2 AMAM f/M CLCL CLCL

9. Parallel Architecture - Example f f f Comparator A>B A B C f/2 Comparator A>B A C f/2 Comparator A>B B C f

10. Summary of Voltage Scaling Examples ArchitectureVoltageArea (Normalized) Power (Normalized) Reference 511 Pipelined 2.91.30.39 Parallel 2.93.40.36 Parallel- Pipelined 23.70.2 (unit: voltage)

11. References A. P. Chandreakasan and R. W. Brodersen, Minimizing Power Consumption in Digital CMOS Circuits, IEEE Proceedings, pp.498-523, April 1995. M. Mehendale and S. D. Sherlekar, VLSI Synthesis of DSP Kernels, Kluwer Academic Publishers, 2001. K. K. Parhi, VLSI Digital Signal Processing Systems – Design and Implementation, John Wiley & Sons, 1999. S.S. Rofail and K. Yeo, Low-Voltage, Low-Power Digital BiCMOS Circutis, Prentice Hall, 2000.