1. CPU Overview Computer Organization II 1 CS@VT February 2009 ©2006-09 McQuain & Ribbens Introduction CPU performance factors – Instruction count n Determined by ISA and compiler – CPI and Cycle time n Determined by CPU hardware We will examine two MIPS implementations – A simplified version – A more realistic pipelined version Simple subset, shows most aspects – Memory reference: lw, sw – Arithmetic/logical: add, sub, and, or, slt – Control transfer: beq, j

2. CPU Overview Computer Organization II 2 CS@VT February 2009 ©2006-09 McQuain & Ribbens Instruction Execution PC  instruction memory, fetch instruction Register numbers  register file, read registers Depending on instruction class – Use ALU to calculate n Arithmetic result n Memory address for load/store n Branch target address – Access data memory for load/store – PC  target address or PC + 4

3. CPU Overview Computer Organization II 3 CS@VT February 2009 ©2006-09 McQuain & Ribbens CPU Overview

4. Computer Organization II 4 CS@VT February 2009 ©2006-09 McQuain & Ribbens Need for Selection Mechanisms Compute address for sequential execution. Compute address for conditional branch. Must choose which one goes back to PC. BUT, you cannot just join wires together to achieve this…

5. CPU Overview Computer Organization II 5 CS@VT February 2009 ©2006-09 McQuain & Ribbens Multiplexor An 2 n x 1 multiplexor receives 2 n input bits and n selector bits, and outputs exactly one of the input bits, determined by the pattern of the selector bits. 2 x 1 multiplexor 4 x 1 multiplexor

6. CPU Overview Computer Organization II 6 CS@VT February 2009 ©2006-09 McQuain & Ribbens Need for Control Logic There must be a combinational circuit that determines which input should be selected and passed through to the PC. The 2x1 multiplexor must have a 1-bit control line to select between the two inputs. So, under when should the conditional address be used? … if we're executing a conditional branch instruction and the condition has evaluated to true.

7. CPU Overview Computer Organization II 7 CS@VT February 2009 ©2006-09 McQuain & Ribbens Control Questions What goes here? What control settings will the ALU need? What's the logic for controlling the other MUXes?

8. CPU Overview Computer Organization II 8 CS@VT February 2009 ©2006-09 McQuain & Ribbens Logic Design Basics Information encoded in binary – Low voltage = 0, High voltage = 1 – One wire per bit – Multi-bit data encoded on multi-wire buses Combinational elements – Operate on data – Output is purely a function of input State (sequential) elements – Store information – Output/state depends on input and on previous state

9. CPU Overview Computer Organization II 9 CS@VT February 2009 ©2006-09 McQuain & Ribbens Combinational Elements AND-gate – Y = A & B A B Y I0 I1 Y MuxMux S Multiplexer – Y = S ? I1 : I0 A B Y + A B Y ALU F Adder – Y = A + B Arithmetic/Logic Unit – Y = F(A, B)

10. CPU Overview Computer Organization II 10 CS@VT February 2009 ©2006-09 McQuain & Ribbens Sequential Elements Register: stores data in a circuit – Uses a clock signal to determine when to update the stored value – Edge-triggered: update when Clk changes from 0 to 1 D Clk Q D Q

11. CPU Overview Computer Organization II 11 CS@VT February 2009 ©2006-09 McQuain & Ribbens Sequential Elements Register with write control – Only updates on clock edge when write control input is 1 – Used when stored value is required later D Clk Q Write D Q Clk

12. CPU Overview Computer Organization II 12 CS@VT February 2009 ©2006-09 McQuain & Ribbens Clocking Methodology Combinational logic transforms data during clock cycles – Between clock edges – Input from state elements, output to state element – Longest delay determines clock period

13. CPU Overview Computer Organization II 13 CS@VT February 2009 ©2006-09 McQuain & Ribbens Building a Datapath Datapath – Elements that process data and addresses in the CPU n Registers, ALUs, mux’s, memories, … We will build a MIPS datapath incrementally – Refining the overview design

14. CPU Overview Computer Organization II 14 CS@VT February 2009 ©2006-09 McQuain & Ribbens Instruction Fetch 32-bit register Increment by 4 for next instruction

15. CPU Overview Computer Organization II 15 CS@VT February 2009 ©2006-09 McQuain & Ribbens R-Format Instructions Read two register operands Perform arithmetic/logical operation Write register result

16. CPU Overview Computer Organization II 16 CS@VT February 2009 ©2006-09 McQuain & Ribbens Load/Store Instructions Read register operands Calculate address using 16-bit offset – Use ALU, but sign-extend offset Load: Read memory and update register Store: Write register value to memory

17. CPU Overview Computer Organization II 17 CS@VT February 2009 ©2006-09 McQuain & Ribbens Branch Instructions Read register operands Compare operands – Use ALU, subtract and check Zero output Calculate target address – Sign-extend displacement – Shift left 2 places (word displacement) – Add to PC + 4 n Already calculated by instruction fetch

18. CPU Overview Computer Organization II 18 CS@VT February 2009 ©2006-09 McQuain & Ribbens Branch Instructions Just re-route wires Sign-bit wire replicated