1. Workshop - November 2011 - Toulouse Paul Brelet TRT paul.brelet@thalesgroup.com Case of smart camera system 24/11/2011 1

2. Introduction Socket Flow. Hardware Design Flow. Tools: SPEAR DE MAGILLEM Tools GAUT 2Workshop - November 2011

3. SoCKET Flow Global SoC Req. SoC Architecture Functional validation SW Performance Validation C/C++/ASM Functionality Fonctionnalité + timing Instruction Set Simulator System Requirements Platform Assembly Metrics HLS System Properties Hardware properties Software properties TLM LT TLM AT Software Co-simulation/Co-emulation Silicon Software Execution HLS Traffic generator Metrics IP-Xact SoC Headers generation RTL Software Requirements traceability 3

4. Phase 2: HW Design Level: RTL. Tools: - GAUT: Apply on accelerator engines. - Magillem: Packager, Platform Assembly, Generator Studio. - SPEAR DE: Mapping Validation : Register Level. Links : - Scripts « bash ». 4Workshop - November 2011

5. Template JET HAL SystemC Skeleton client GAUT VHDL Acc. client TE IP-XACT library PLT Assembly MDS Spear Application Netlister MDS Vhdl FPGA MRV Generator Generator Studio Generic client Validation Thales Flow: RTL Validation 5

6. SPEAR Tool 6Workshop - November 2011

7. SPEAR: Application Application catching 7Workshop - November 2011

8. SPEAR: Application Change the I/O: Fitting/paving Automatic cornerturn 8Workshop - November 2011

9. SPEAR: Architecture Architecture Model 9Workshop - November 2011

10. Mapping SPEAR Application mapping 10Workshop - November 2011

11. SPEAR: Code generation Code generation 11Workshop - November 2011

12. TLM Simulation 12Workshop - November 2011

13. MAGILLEM Tool RTL Level: - Bus interface, components creation, link between components: ditto TLM. VHDL code generation: - Using generics. - The code is readable by an individual. - Inter-connects are taken into account during the VHDL code generation. 13Workshop - November 2011

14. GAUT Tool The C code: - The C code must be very close to VHDL code. Comparison with commercial tools: - Roccc, ImpulseC. Some troubles during VHDL code generation: - The generated code can be synthesizable but it does not work well in placement/routing. 14Workshop - November 2011

15. IP-XACT Advantage Standard: Reuse strategy Support of SystemC Model by TLM ports Opportunities for “bottom up” and “top down” XML Transformation: correct and complete XML descriptions Hardware description: lot of data for several components 15Workshop - November 2011

16. Questions? 16Workshop - November 2011