1. VHDL ELEC 311 Digital Logic and Circuits Dr. Ron Hayne Images Courtesy of Cengage Learning

2. 311_102 VHDL Tools  Hardware Description Language Tools Text Editor Design Entry Compiler Syntax Simulator Test Bench Functional Verification Synthesis tool Libraries Target Technology

3. 311_103 VHDL Model  Entity Component interface Inputs Outputs  Architecture Structural Dataflow Behavioral

4. Propagation Delays 311_104

5. Std_Logic_Vectors 311_105

6. Multiplexers 311_106

7. Design Hierarchy 311_107

8. 8 4-bit Ripple-Carry Adder entity Adder4 is port(A, B: in std_logic_vector(3 downto 0); Ci: in std_logic; S: out std_logic_vector(3 downto 0); Co: out std_logic); end Adder4;

9. 311_109 VHDL Types  Predefined Types  IEEE Standard Logic

10. 311_1010 VHDL Operators & concatenation

11. 311_1011 VHDL Libraries and Packages  library IEEE;  use IEEE.std_logic_1164.all; Types std_logic and std_logic_vector  use IEEE.std_logic_unsigned.all; Overloaded operators Conversion functions  use work.project3_gates.all;

12. 311_1012 Project 3 VHDL  Structural Description Entity Structural Architecture  Package Component declarations Dataflow descriptions

13. 311_1013 Project 3 Xilinx  New Project Top-Level Source Type → HDL  Project → New Source VHDL Module  Project → Add Copy of Source project3_gates.vhd

14. New Source 311_1014

15. 311_1015

16. Summary  Entity  Architecture Structural Dataflow Behavioral  Types  Operators  Libraries and Packages 311_1016