1. CSCE 211 Digital Design Lecture 12 Registers
Topics
Flip-flop review
Debouncing
Registers
Readings
November 4, 2015

2. Overview: Last Time: Excitation tables
New: a collection of things revisited
Two bit Adder
Things from last Lecture (Lec12):
Flip-flop: Characteristic tables and excitation tables
Counters
Parallel Load
Next Time
Two bit counter
Homework

3. Flip-flop: Characteristic/Excitation Tables (Review)
Transition (Characteristic) table - next state as function of inputs and current state
Excitation table – inputs required to cause specified transition

4. Convert SR Master-slave to J-K Flip Flop

5. 2 Bit Adder Circuit Sums-of-products Products-of-sums Logic diagram
Chiplist gate mapping
Wiring diagram

6. F(W,X,Y,Z) = Σ (0,2,3,5,6,8,9) X WX YZ 00 01 11 10 4 12 8 1 5 13 9 Z 3 7 15 11 Y 6 14 10 2 W

7. F(W,X,Y,Z) = Σ (0,2,3,5,6,8,9) X WX YZ 00 01 11 10 4 12 8 1 5 13 9 Z 3 7 15 11 Y 6 14 10 2 W

8. F(W,X,Y,Z) = Σ (0,2,3,5,6,8,9) X WX YZ 00 01 11 10 4 12 8 1 5 13 9 Z 3 7 15 11 Y 6 14 10 2 W

9. 74LS139 Decoder Dual 2x4 decoder

10. Using a 74LS139 to implement a Half-adderX Y S C

11. 74LS112 – Dual Neg Edge JK flip flop9 9 9 9 9 9 9 9 9 9 9 9 9 9 9 9 K J
CLR
Pre Q Q

12. 74LS00
74LS10
74LS05
74LS112
74LS30

13. Google(debouncing switch images)

14. Counters
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
Increment first –
control line 0no change; 1  increment
4-bits  4 flip-flops, say A3A2A1A0
T flip-flops complement of no change
When do we complement?

15. decrement

16. Counter using 74LS112 – Dual Neg Edge JK flip flop

17. Parallel Load registers with JK flip flops

18. Dual cutoff of control lines
What happens if load = 1 and Increment = 1 at the same time?
Priority cutoff

19. Counters + parallel load

20. State-machine structure (Mealy)
output depends on state and input
typically edge-triggered D flip-flops

21. State-machine structure (Moore)
output depends on state only
typically edge-triggered D flip-flops

22. TBird Lights
State machine problem

23. TBird Lights