1. PART 4: (1/2) Central Processing Unit (CPU) Basics CHAPTER 12: P ROCESSOR S TRUCTURE AND F UNCTION

2. CPU Structure CPU must: – Fetch instructions – Interpret (Decode) instructions – Fetch data – Process data – Write data

3. CPU With Systems Bus

4. CPU Internal Structure

5. Registers CPU must have some working space (temporary storage) Called registers Number and function vary between processor designs One of the major design decisions Top level of memory hierarchy

6. User Visible Registers General Purpose Data Address Condition Codes

7. General Purpose Registers (1) May be true general purpose May be restricted May be used for data or addressing Data – Accumulator Addressing – Segment

8. General Purpose Registers (2) Make them general purpose – Increase flexibility and programmer options – Increase instruction size & complexity Make them specialized – Smaller (faster) instructions – Less flexibility

9. How Many GP Registers? Between 8 - 32 Fewer = more memory references More does not reduce memory references and takes up processor real estate See also RISC

10. How big? Large enough to hold full address Large enough to hold full word Often possible to combine two data registers – C programming – double int a; – long int a;

11. Condition Code Registers Sets of individual bits – e.g. result of last operation was zero Can be read (implicitly) by programs – e.g. Jump if zero Can not (usually) be set by programs

12. Control & Status Registers Program Counter Instruction Decoding Register Memory Address Register Memory Buffer Register Revision: what do these all do?

13. Program Status Word A set of bits Includes Condition Codes Sign of last result Zero Carry Equal Overflow Interrupt enable/disable Supervisor

14. Supervisor Mode Intel ring zero Kernel mode Allows privileged instructions to execute Used by operating system Not available to user programs

15. Other Registers May have registers pointing to: – Process control blocks (see O/S) – Interrupt Vectors (see O/S) N.B. CPU design and operating system design are closely linked

16. Example Register Organizations

17. Data Flow (Instruction Fetch) Depends on CPU design In general: Fetch – PC contains address of next instruction – Address moved to MAR – Address placed on address bus – Control unit requests memory read – Result placed on data bus, copied to MBR, then to IR – Meanwhile PC incremented by 1

18. Data Flow (Fetch Diagram) 1 2 3 4 4 5 6 7

19. Data Flow (Data Fetch) IR is examined If indirect addressing, indirect cycle is performed – Right most N bits of MBR transferred to MAR – Control unit requests memory read – Result (address of operand) moved to MBR

20. Data Flow (Indirect Diagram) 1 2 3 4 4 5 6

21. Indirect Cycle May require memory access to fetch operands Indirect addressing requires more memory accesses Can be thought of as additional instruction sub-cycle

22. Instruction Cycle with Indirect

23. Data Flow (Execute) May take many forms Depends on instruction being executed May include – Memory read/write – Input/Output – Register transfers – ALU operations

24. Instruction Cycle (with Interrupts) - State Diagram

25. Data Flow (Interrupt) Simple Predictable Current PC saved to allow resumption after interrupt Contents of PC copied to MBR Special memory location (e.g. stack pointer) loaded to MAR MBR written to memory PC loaded with address of interrupt handling routine Next instruction (first of interrupt handler) can be fetched

26. Data Flow (Interrupt Diagram)

27. Prefetch Fetch accessing main memory Execution usually does not access main memory Can fetch next instruction during execution of current instruction Called instruction prefetch

28. Improved Performance But not doubled: – Fetch usually shorter than execution Pre-fetch more than one instruction? – Any jump or branch means that prefetched instructions are not the required instructions Add more stages to improve performance

29. PART 4: (2/2) Processor Internals CHAPTER 19: CONTROL UNIT OPERATION 29

30. Micro-Operations A computer executes a program Fetch/execute cycle Each cycle has a number of steps – Eg: Fetch Instruction, Decode, Fetch Operand, Execute, Write Called micro-operations Each step does very little Atomic operation of CPU 30

31. Constituent Elements of Program Execution 31

32. Fetch - 4 Registers Memory Address Register (MAR) – Connected to address bus – Specifies address for read or write op Memory Buffer Register (MBR) – Connected to data bus – Holds data to write or last data read Program Counter (PC) – Holds address of next instruction to be fetched Instruction Register (IR) – Holds last instruction fetched 32

33. Data Flow (Fetch Diagram) 1 2 3 4 4 5 6 7

34. Fetch Sequence Address of next instruction is in PC Address (MAR) is placed on address bus Control unit issues READ command Result (data from memory) appears on data bus Data from data bus copied into MBR PC incremented by 1 (in parallel with data fetch from memory) Data (instruction) moved from MBR to IR MBR is now free for further data fetches 34

35. Sequence of Events, Fetch Cycle 35 Address of next instruction is in PC Address (MAR) is placed on address bus Data from data bus copied into MBR PC incremented by 1 Data (instruction) moved from MBR to IR

36. Fetch Sequence (symbolic) t1:MAR <- (PC) t2:MBR <- (memory) PC <- (PC) +1 t3:IR <- (MBR) OR t1:MAR <- (PC) t2:MBR <- (memory) t3:PC <- (PC) +1 IR <- (MBR) (tx = time unit/clock cycle) () = what’s inside 36

37. Rules for Clock Cycle Grouping Proper sequence must be followed – MAR <- (PC) must come before MBR <- (memory) – (memory) need to know the address from (MAR) first Conflicts must be avoided – Must not read & write same register at same time – MBR <- (memory) & IR <- (MBR) must not be in same cycle Also: PC <- (PC) +1 involves addition – Use ALU – May need additional micro-operations 37

38. Indirect Cycle MAR <- (IR address ) - address field of IR MBR <- (memory) IR address <- (MBR address ) MBR contains an address IR is now in same state as if direct addressing had been used 38

39. Interrupt Cycle t1:MBR <-(PC) //after finish interrupt, return to the old PC, now in MBR t2:MAR <- save-address PC <- routine-address t3:memory <- (MBR) This is a minimum – May be additional micro-ops to get addresses – N.B. saving context is done by interrupt handler routine, not micro-ops 39

40. Execute Cycle (ADD) Different for each instruction e.g. ADD R1,X - add the contents of location X to Register 1, result in R1 t1:MAR <- (IR address ) t2:MBR <- (memory) t3:R1 <- R1 + (MBR) Note no overlap of micro-operations 40

41. Execute Cycle (ISZ) ISZ X - increment and skip if zero – t1:MAR <- (IR address ) – t2:MBR <- (memory) – t3:MBR <- (MBR) + 1 – t4:memory <- (MBR) – if (MBR) == 0 then PC <- (PC) + 1 Notes: – if is a single micro-operation – Micro-operations done during t4 41

42. Execute Cycle (BSA) BSA X - Branch and save address – Address of instruction following BSA is saved in X – Execution continues from X+1 – t1:MAR <- (IR address ) – MBR <- (PC) – t2:PC <- (IR address ) – memory <- (MBR) – t3:PC <- (PC) + 1 42

43. 10 minutes Break.... 43

44. Instruction Cycle Each phase decomposed into sequence of elementary micro-operations E.g. fetch, indirect, and interrupt cycles Execute cycle – One sequence of micro-operations for each opcode Need to tie sequences together Assume new 2-bit register – Instruction cycle code (ICC) designates which part of cycle processor is in 00: Fetch 01: Indirect 10: Execute 11: Interrupt 44

45. 45 Flowchart for Instruction Cycle

46. Functional Requirements Define basic elements of processor Describe micro-operations processor performs Determine functions control unit must perform 46

47. Basic Elements of Processor ALU Registers Internal data paths External data paths Control Unit 47

48. Types of Micro-operation Transfer data between registers Transfer data from register to external Transfer data from external to register Perform arithmetic or logical ops 48

49. Functions of Control Unit Sequencing – Causing the CPU to step through a series of micro- operations Execution – Causing the performance of each micro-op This is done using Control Signals 49

50. Control Signals Clock – One micro-instruction (or set of parallel micro-instructions) per clock cycle Instruction register – Op-code for current instruction – Determines which micro-instructions are performed Flags – State of CPU – Results of previous operations From control bus – Interrupts – Acknowledgements 50

51. Model of Control Unit 51

52. Control Signals - output Within CPU – Cause data movement – Activate specific functions Via control bus – To memory – To I/O modules 52

53. Example Control Signal Sequence - Fetch MAR <- (PC) – Control unit activates signal to open gates between PC and MAR MBR <- (memory) – Open gates between MAR and address bus – Memory read control signal – Open gates between data bus and MBR 53

54. Data Paths and Control Signals 54

55. Example Control Signal Sequence - Fetch MAR <- (PC) – Control unit activates signal to open gates between PC and MAR 55

56. Example Control Signal Sequence - Fetch MBR <- (memory) – Open gates between MAR and address bus – Memory read control signal – Open gates between data bus and MBR 56

57. Internal Organization Usually a single internal bus Gates control movement of data onto and off the bus Control signals control data transfer to and from external systems bus Temporary registers needed for proper operation of ALU 57

58. CPU with Internal Bus 58

59. Intel 8085 CPU Block Diagram 59

60. Intel 8085 Pin Configuration 60

61. Intel 8085 OUT Instruction Timing Diagram 61

62. Hardwired Implementation (1) Control unit inputs Flags and control bus – Each bit means something Instruction register – Op-code causes different control signals for each different instruction – Unique logic for each op-code – Decoder takes encoded input and produces single output – n binary inputs and 2 n outputs 62

63. Hardwired Implementation (2) Clock – Repetitive sequence of pulses – Useful for measuring duration of micro-ops – Must be long enough to allow signal propagation – Different control signals at different times within instruction cycle – Need a counter with different control signals for t1, t2 etc. 63

64. Control Unit with Decoded Inputs 64

65. Problems With Hard Wired Designs Complex sequencing & micro-operation logic Difficult to design and test Inflexible design Difficult to add new instructions 65