1. Low-Power and High-Speed Interconnect Using Serial Passive Compensation Chun-Chen Liu and Chung-Kuan Cheng Computer Science and Engineering Dept. University of California, San Diego http://www.cse.ucsd.edu/~kuan/

2. Outline Motivation Previous Works and Our Contributions Proposed Passive Compensation Technique  Theory  Experiments: An MCM stripline Case Analytical Performance Prediction Experimental Results and Future Work

3. Motivation Technology Advancement: Interconnect is one bottleneck of system performance. Bandwidth Increase: Interchip communication is expected to exceed 15GHz in 2010. Low Power Requirement: IO consumes one major portion of chip power budget.

4. Previous Works Overview On-chip serial link signaling schemes  Pre-emphasis and equalization (W. Dally, ’98)  Clocked discharging (Horowitz, ISVLSI’03)  Frequency modulation (Wong, JSSC’03, Jose, ISVLSI‘05)  Non-linear transmission line (Hajimiri, JSSC’05, E. C. Kan, CICC’05) Passive compensation  Resistive termination (Hashimoto, EPEP’04, Tsuchiya, CICC’04, Flynn, ICCAD’05, CICC’05)  Surfliner (C.K Cheng, ASPDAC’07)

5. Published on-chip serial link signaling schemes- Resistive Termination Use resistive termination to cut the slow RC top Michael Flynn, ICCAD ‘05 Tsuchiya et al. developed an analytical model of eye opening with resistive termination for on-chip transmission line (CICC ’05)

6. Published on-chip serial link signaling schemes- Surfliner Use shunt resistors to reduce loss tangent and maximize eye-opening and minimize jitters. Haikun Zhu et al. developed an analytical model for eye opening with shunt resistors. Haikun Zhu et al. Aspdac ’ 07

7. Our Contributions The main advantages of this work  Adopt a novel serial passive impedance scheme to reduce the power consumption and improve the bandwidth.  Derive eye prediction methods using bitonic assumption.  Propose a new interconnect scheme with wide band working frequency. Our proposed scheme  MCM interconnect using parallel resistor and capacitor as equalizer.

8. Problem Formulation and Design Flow Problem Formulation  Input: T line with R(f), L(f), G(f), C(f) (IBM EIP).  Output: Best Z d to maximize the eye diagram. Design Flow 1.Set R d = R skin - R dc, 2.Repeat steps 3, 4 with tuned C d to maximize eye-opening 3.Generate step response using HPSICE. 4.Predict eye diagram using step response.

9. Theory Analytical -Bitonic Step Response Assumption Bitonic step response assumption  A step response that monotonically increases to its peak and then monotonically decreases to saturation voltage.  We use three parameters V 1, V max and V sat to predict the eye diagram.

10. Theoretical Analysis Telegrapher’s equations Propagation Constant Wave Propagation and correspond to attenuation and phase velocity. Both are frequency dependent in general. Characteristic Impedance

11. Implementation Interconnect Scale On-chipMCMBoard Length10mm10cm25cm Series Resistance at DC 10Ω/mm1Ω/mm0.01Ω/mm Cross Section Dimension 1μmx1μm8μmx4.5μm4milx1.2mil Dielectric MaterialS i O2CeramicFR4 Dielectric Constant3.93.4 Loss Tangent0.000680.00180.016 Frequency dependency SmallLargeSignificant Operation RegionRCRLC Skin depth of pure copper 0.66 μm @ 10GHz

12. Experiment Setting: Geometry is based on IBM high-end AS/400 system. Line length = 10 cm.

13. Step Response with R d and R t (10 segments)

14. Step Response with R t (10 segments)

15. Step Response with Z d and R t (10 segments)

16. Eye-height/jitter vs R d and C d (10Gbps)

17. Eye Diagram – Z d, R t 30Gbps with C d =0.41e-12, R d =141, R t =74 V height = 0.303V, Jitter; 2.41ps

18. Eye Diagram- Z d, R t 40 Gbps with C d =0.31e-12, R d =168, R t =74 V height = 0.23V, Jitter= 2.1ps

19. Eye Diagram- Z d, R t 50 Gbps, with C d =3e-13, R d =193, R t =74 V height = 0.21V, Jitter= 4.21ps

20. Eye Diagrams- Z d, R t 100 Gbps with C d =1e-13, R d =247, R t =74 Non-Distinguishable

21. Eye Diagrams - R t 30Gbps with R d = 0, R t =70 V height = 0.188V, Jitter= 13.78ps

22. Eye Diagrams - R t 40Gbps with R d = 0, R t =70 V height = 0.07V, Jitter= 15.59ps

23. Eye Diagrams – R d, R t 10Gbps, R d =74, V height = 0.269V, jitter=7.03ps

24. Eye Diagrams – R d, R t 20Gbps, R d =74 V height = 0.163V, jitter=10.04ps

25. Eye Diagrams – R d, R t 30Gbps, R d =74 V height = 0.103V, jitter=15.01ps

26. Eye Diagrams – R d, R t 40Gbps, R d =74 V height = 0.043V, jitter=16.2ps

27. Experimental Results R d = R skin -R dc, R dc =50ohm

28. Optimal solution, and power consumption comparison Achieve lowest power consumption. Reach up to 50Gbps with open eyes.

29. Compared predicted Eye-high with HSPICE

30. Future Work Automate the synthesis. Prototype & measurement. Incorporate transmitter/receiver. Applications: clock trees, buses.

31. Q/A Thank You