1. COMP541 Memories II: DRAMs
Montek Singh
Oct 19, 2015

2. Topics Last lecture: Today: Read-Only Memories (ROMs)
Static Random-Access Memory (SRAM)
Today:
Dynamic Random-Access Memory (DRAM)

3. Dynamic RAM (DRAM) Very “lightweight” bit-level memory
a single capacitor holds charge (= value)
no charge = ‘0’
a single transistor acts as gate
Write: connect switch & add charge to store a ‘1’…
… then disconnect switch
Read: read by connecting switch

4. DRAM Bit Cell Very lightweight contrast with SRAM
DRAM cell consists of one transistor and one capacitor!
SRAM cell has at least 6 transistors
DRAM bit cell:
SRAM bit cell:

5. Hydraulic Analogy: Writing
Storage
Full (1)
Empty (0)
Pump fills tank to 1 value
Pump drains tank to 0 value

6. Hydraulic Analogy: Reading
Outside water begins at intermediate level (black wavy line)
Tank had a 1 value – raises water level
Tank had a 0 value – lowers water level

7. DRAM Characteristics Destructive Read Refresh
When cell is read, charge is (partially) removed
Must be restored after each read!
Refresh
Also, there’s steady leakage
and no transistor to constantly automatically replenish
Charge must be restored periodically

8. DRAM Logical Diagram
Control circuitry
Core memory storage

9. Delay until data available
DRAM Read Signaling
Since DRAM is often on a separate chip
number of pins available can be a limitation
lower pin count by using same pins for row and column addresses
Delay until data available

10. DRAM Write Signaling

11. DRAM Refresh Many strategies refresh circuits on chip
here a simple row counter: reads and writes back

12. Refresh Timing Say, need to refresh every 64ms Distributed refresh
Spread refresh out evenly over 64ms
Say on a DRAM with 8192 rows (213), refresh window for each row = 64ms/8192=7.8 us
Assume: time to refresh each row is 30ns
Total time spent in refresh = 30ns * 8192 = 0.25ms
but spread out
Burst refresh
Same 0.25ms, but all at once
May not be good in a computer system
an unlucky instruction will have to wait long…
Refresh takes low % of total time
0.25 ms / 64 ms = less than 4%

13. Bidirectional Lines Another optimization for reducing pins:
Many chips have one set of data pins
same pins used as data input for write operations
same pins used as data output for read operations
otherwise float them (i.e., tri-state)
Makes sense because don’t need both read/write data at once

14. Synchronous DRAM (SDRAM)
Has a clock
Common type in PCs late-90s
Typical DRAMs still synchronous
Multiple banks
Pipelined
Start read in one bank after another
Come back and read the resulting values one after another

15. Modes of DRAM operation
DRAMs optimized to read & write entire blocks
or at least a few consecutive locations
Several different modes
normal/basic mode
Nibble or Burst Mode
Fast Page Mode
Extended Data Out (EDO) Mode

16. Basic Mode of Operation
Row
Column
Address
RAS
CAS
Data
Slowest mode
Uses only single row and column address
Row access is slow (60-70ns) compared to column access (5-10ns)
Leads to three techniques for DRAM speed improvement
Getting more bits out of DRAM on one access given timing constraints
Pipelining the various operations to minimize total time
Segmenting the data in such a way that some operations are eliminated for a given set of accesses

17. Nibble (or Burst) Mode Several consecutive columns are accessed
RAS
CAS CAS CAS CAS
RA CA
D1 D2 D3 D4
Several consecutive columns are accessed
Only first column address is explicitly specified
Rest are internally generated using a counter

18. Fast Page Mode Accesses arbitrary columns within same row
RAS
CAS CAS CAS CAS
RA CA1 CA2 CA3 CA4
D1 D2 D3 D4
Accesses arbitrary columns within same row
Static column mode is similar

19. EDO Mode Arbitrary column addresses Pipelined EDO = Extended Data Out
RAS
CAS CAS CAS CAS CAS CAS CAS
RA CA1 CA2 CA3 CA4 CA5 CA6 CA7
D1 D2 D3 D4 D5 D6
Arbitrary column addresses
Pipelined
EDO = Extended Data Out
Has other modes like “burst EDO”, which allows reading of a fixed number of bytes starting with each specified column address

20. DDR DRAM Double Data Rate (DDR) SDRAM
Transfers data on both edges of the clock
Currently popular
You get two memory accesses per clock cycle!

21. RAMBUS DRAM (RDRAM) Another attempt to alleviate pin limits
Many (16-32) banks per chip
Made to be read/written in packets
Up to 1200MHz bus speeds
XDR – 8 bits per clock, 16-bit wide bus, 6.4GB
But DDR doing very well also
Quite expensive
almost disappeared from consumer PCs
still present in servers and specialized chips

22. DRAM Controllers
Very common to have a separate chip/module that controls memory
Handles banks
Handles refresh
Multiplexes column and row addresses
RAS and CAS timing
Called “Northbridge” on PC chip set

23. Conclusions RAMs with different characteristics Static RAM Dynamic RAM
For different purposes
Static RAM
Simple to use, small, expensive
Fast, used for cache
Dynamic RAM
Complex to interface, largest, cheap
Needs periodic refresh

24. Links Ram Guides (not very technical) Your Nexys 4 board manual
Your Nexys 4 board manual