2. CLASSICAL LOGIC 2

3. 3

4. 4

5. 5 SRFPGA layout With I/O pins

6. 6 Var1 var2 var3 var4 var5 var6 var7 var8 var9 var10 var11 var12 var13 var14 var15 var16 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 1 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 1 1 1 1 1 1 1 1 1 1 1 1 0 Input test vector InputtestvectorInputtestvector Test output TestoutputTestoutput Faults observed during column test C = 2. Faults observed during diagonal test D = 2 Total number of Faults N = C * D = 2 * 2 = 4.

7. REVERSIBLE LOGIC 7

8. A logic gate is reversible if  Each input is mapped to a unique output  It permutes the set of input values A combinational logic circuit is reversible if it satisfies the following:  Has only one Fanout,  Uses only reversible gates,  No feedback path,  has as many input wires as output wires, and permutes the input values. 8

9. 9 NOT gate a b a c 0 0 0 1 1 0 1 1 1 1 1 0 Controlled-NOT or Feynman gate

10. 10 a b c a b f 0 0 0 0 0 1 0 1 0 0 1 1 1 0 0 1 0 1 1 1 0 1 1 1 1 1 1 1 1 0 Toffoli gate (Controlled-Controlled NOT gate)

11. 11 Swap gate Implementation of Swap gate using controlled-NOT

12. 12 Swap gate Implementation of Swap gate using controlled-NOT

13. 13 a b c a f g 0 0 0 0 0 1 0 1 0 0 1 1 1 0 0 1 0 1 1 1 0 1 1 0 1 0 1 1 1 1 Fredkin gate (Controlled SWAP gate)

14. 14

15. MMD: Transformation based Gupta-Agrawal-Jha: PPRM based Mishchenko-Perkowski: Reversible wave cascade Kerntopf: Heuristics based Wille: BDD based synthesis 15

16. 16 c b ac o b o a o 0 0 00 0 1 0 0 0 0 1 01 1 1 0 1 10 1 0 1 0 00 0 1 1 0 11 0 0 1 1 01 0 1 1 1 11 1 0  PPRM form for each output in terms of Input variables are given as follows and node is created  PPRM form for each output in terms of Input variables are given as follows and node is created

17. Parent node is explored by examining each output variable in the PPRM expansion. Factors are searched in the PPRM expansions that do not contain the same input variable. For example in the expansion below appropriate terms are “c” and “ac” The substitution is performed as In this example OR 17

18. 18

19. 19 New nodes are created based on substitution

20. 20

21. 21

22. 22

23. Common problem with current approaches: they invariably use nxn Toffoli gates, that might imposes technological limitations. High Quantum cost of Toffoli gates with many inputs. Synthesize only reversible functions, not Boolean functions that is not reversible. 23

24. 24  Implementation of 4x4 Toffoli gate with Quantum realizable 2x2 primitives such as controlled-V, controlled-NOT, controlled-V +.

25. CREATING QUANTUM ARRAY FROM LATTICE 25

26. 26 Positive Davio Tree can be created by expanding PPRM function using positive Davio expansion. Positive Davio Lattice is created by performing joining operation for neighboring cells at every level. Other Lattices can be created using similar method but using expansions such as Shannon or Negative Davio expansions or combination of them.

27. On the previous foils I showed representation of the Davio and Shannon cells as cascade of reversible gates. Next I present unique method to create Quantum Array from Positive Davio Lattice. The same approach can be used for other Lattices. 27

28. 28  Each node represents pDv cell.

29. 29 + + + + + + + + + 0 d 1 1 1 1 1 1 1 1 1 11 1 1 d a d b b 1 a a c 1

30. 30 a b c d 0 1 1 1 0 1 a1  ad1  bab1  d a aabdb  adabddb1  bddab  bcdcdacbcabdaddb1  garbage function

31. 31 a b c d 0 1 1 1 0 1 a1  ad1  bab1  d a aabdb  adabddb1  bddab  bcdcdacbcabdaddb1  garbage function

32. 32  Each node represents pDv cell.

33. 33

34. Reversible circuit synthesized with only 3x3 Toffoli gates. Generates reversible circuit for any ESOP. Adds ancilla bits but overall cost of the circuit will be lower due to use of low cost 3x3 Toffoli gates. 34

35. 35

36. 36

37. 37

38. DIPAL GATES, DIPAL GATE FAMILIES AND THEIR ARRAYS 38

39. 39

40. 40 a b c cabaf  a b c cabaf  cb  a Shannon cell Dipal cell representation with reversible gates  There are 2 3 ! = 8! = 40320 3x3 Reversible logic functions, however only handful of them shown earlier are useful for synthesis purpose.  Dipal gate is a reversible equivalent of Shannon cell  Dipal gate is a reversible equivalent of Shannon cell

41. 41 a b c bacaf  a b c a cb  bacaf  Shannon cell with negative variable Dipal cell with negative variable represented with reversible gates

42. 42 a b c cabaf  a b c cabaf  cb  a Shannon cell Dipal cell representation with reversible gates  There are 2 3 ! = 8! = 40320 3x3 Reversible logic functions, however only handful of them shown earlier are useful for synthesis purpose.  Dipal gate is a reversible equivalent of Shannon cell  Dipal gate is a reversible equivalent of Shannon cell

43. cbaa 000000 001001 010110 011101 100100 101111 110010 111011 43 inputoutput 00 11 26 35 44 57 62 73

44. 44 000 001 010 011 100 101 110 111 000 001 010 011 100 101 110 111

45. 45

46. EXPERIMENTAL RESULTS 46

47. 47 Benchmark#Real inputs #Garbag e inputs #Gates Lattice Cost Lattice CPU time Lattice #Gates DMM Cost DMM #Gates AJ Cost AJ 2to554311070.121510720100 rd323148< 0.014848 rd53551139< 0.01167513116 3_17311021< 0.01612614 6sym106341500.372062NA 5mod5511458< 0.0110901191 4mod541618< 0.015135 ham33037< 0.015759 xor55044< 0.014444 Xnor55155< 0.01------------------ decod24421030< 0.01------------------1131 Cycle10_212618086027.9191198---------- ham77522580.1023812468

48. 48 Benchmark#Real inputs #Garbage inputs #Gates Lattice Cost Lattice CPU time Lattice #Gates DMM Cost DMM #Gates AJ Cost AJ graycode66555< 0.015555 graycode1010999< 0.019999 graycode202019 < 0.0119 nth_prime3_ inc 3446< 0.0146---------- nth_prime4_ inc 451648< 0.011258---------- nth_prime5_ inc 5529910.222678---------- alu52517< 0.01------------------18114 4_494416520.0416581361 hwb4441228< 0.0117631535 hwb55524961.224104---------- hwb666321282.042140---------- pprm144933< 0.01------------------

49. 49 Benchmark#Inputs#Gates pDv Lattice Cost pDv Lattice #Gates Shannon Lattice Cost Shannon Lattice 2to553110741117 rd3234848 rd53511391846 3_17310211526 6sym103415051167 5mod5514583081 4mod546181224 Ham3337610 xor554444 Xnor555555 Decod24410302040 Cycle10_212180860270950 Ham7722583268

50. 50 Benchmark#Inputs#Gates pDv Lattice Cost pDv Lattice #Gates Shannon Lattice Cost Shannon Lattice Graycode665555 Graycode10109999 Graycode202019 nth_prime3_ inc 34668 nth_prime4_ inc 416482961 nth_prime5_ inc 5299139101 Alu55171022 4_49416522258 Hwb4412281531 Hwb55249638110 Hwb663212840134 Pprm149331438

51. 51

52. 52

53.  Fig. 2. Circuit for function FX2 created with our method for traditional cost function calculation that does not take Ion Trap technology constraints into account. 53

54.  Fig. 3. Circuit from Figure 2 modified with adding SWAP gates for new cost function calculation that does take Ion Trap technology constraints into account, with XX gates added. It has 36 SWAP gates added to realize LNNM. 54

55. 55 Example of Positive Davio Lattice from [Perkowski97d]. Positive Davio Expansion is applied in each node. Variable d is repeated

56. 56 Transformation of function F3(a,b,c) from classical Positive Davio Lattice to a Quantum Array with Toffoli and SWAP gates. Each SWAP gate is next replaced with 3 Feynman gates.(a) intermediate form, (b) final Quantum Array.

57. 57

58. 58

59. 59  General layout of the layered diagram  Each box represents a gate from family of Dipal gate

60. 60

61. 61 Benchmark#Gates Lattice Cost Lattice #Gates with SWAP insertion for Lattice Cost with SWAP gates for Lattice #Gates DMM Cost DMM #Gates with SWAP insertion for MMD Cost with SWAP gates for MMD 2to531107611971510731155 rd324882048614 rd53113944138167572273 3_1710211433612818 6sym3415056216206278236 5mod514581767109048204 4mod561810305131131 Ham3373757713 Xor544444444 Xnor55555-------- decod2410301442-------- Cycle10_218086030612381911981991738 Ham7225830112238179249

62. 62 Benchmark#Gates Lattice Cost Lattice #Gates with SWAP insertion for Lattice Cost with SWAP gates for Lattice #Gates DMM Cost DMM #Gates with SWAP insertion for MMD Cost with SWAP gates for MMD Graycode655555555 Graycode1099999999 Graycode2019 Nth_prime3 _inc 465946612 Nth_prime4 _inc 1648206012581876 Nth_prime5 _inc 2991391212678128384 Alu517723-------- ---------- 4_49165241127165840130 hwb412281540176339129 hwb52496441562410464224 hwb6321287224842140144446 pprm19331963-------- ----------

63. GENERALIZED REGULARITIES FOR QUANTUM AND NANO- TECHNOLOGIES 63

64. 64 (a)(b)(c) (d)

65. 65

66. 66

67. 67

68. 68

69. 69

70. 70

71. 71

72. 72

73. 73

74. QUANTUM CIRCUITS AND QUANTUM ARRAYS FROM TRULY QUANTUM GATES 74

75. Basic single qubit quantum gates 75

76.  Transformation of the circuit realized in Fig. 7 using Toffoli gate. Each Toffoli and SWAP gates are replaced by quantum CNOT and CV/CV+ quantum gates and rearranged to satisfy the neighborhood requirements of Ion trap.  76

77.  The transformations of blocks of quantum gates to the pulses level.  77

78. CONCLUSIONS 78

79. Experimental results proved that our algorithm produced better results in terms of quantum cost compared to other contemporary algorithms for synthesis of reversible logic. New gate family called Dipal gate Presented new synthesis method with layered diagrams. More accurate technology specific cost model for 1D qubit neighborhood architecture. 79

80. A new method based of lattice diagram to synthesize reversible logic circuit with 3x3 Toffoli gates. A new method based of lattice diagram to synthesize reversible logic circuit with 3x3 Toffoli gates. A new family of gates called Dipal Gates. A new family of gates called Dipal Gates. New diagrams called layered diagram that uses family of Dipal gate for synthesis of reversible logic function. New diagrams called layered diagram that uses family of Dipal gate for synthesis of reversible logic function. Software for creating Lattice diagrams and software for creating quantum array from Lattice (Lattice to QA). Software for creating Lattice diagrams and software for creating quantum array from Lattice (Lattice to QA). Program to implement a variant of MMD algorithm. Program to implement a variant of MMD algorithm. 80