1. 1 R/2R DAC w/ SPI interface for the IBM 130nm Process Larry Ruckman Physics 476 28April2010

2. 2 Motivation Want to have a digitally controlled voltage reference that’s exactly referenced to the ASIC VDD Increase electronic packing density by stuffing the DAC into the ASIC Decrease production cost by not having to buy DAC ICs from a semiconductor company

3. 3

4. 4 Overall Block Diagram R/2R Ladder 12x REGsSPI STRB GEN

5. 5 R/2R Ladder

6. 6 DAC_BIT

7. 7 12 Bit Simulation LSB = (1.2 V)/(2^12) = 293 mV/count Theoretical slope agrees with simulation Slope errors in measurement will come from fabrication tolerances/errors

8. 8 SPI Timing and REGs

9. 9 Serial Protocol Interface (SPI) AD5324 DAC SPI example Timing Diagram

10. 10 My DAC’s SPI Timing Diagram

11. 11 STRB Timing Simulation Check

12. 12 DAC w/ SPI REGs Layout 129.07 um by 51.23 um Uses 1176 transistors in this design

13. 13 Status/Summary Top Level of my design (test structure) has passed both design checks –LVS = Assura –DRC = Calibre Pin Count: 3 Analog, 3 Digital Inputs = Total 6 Space Requirement: 129.07 um by 51.23 um