1. B.Satyanarayana Department of High Energy Physics Tata Institute of Fundamental Research Homi Bhabha Road, Colaba, Mumbai, 400 005 E-mail: bsn@tifr.res.inbsn@tifr.res.in Status report on electronics, trigger and data acquisition system for the proposed INO prototype detector

2. B.Satyanarayana VECC, Kolkata December 24, 20052 INO prototype detector Detector and signal specifications –Detector dimensions: 1m X 1m X 1m –14 layers of RPCs with 6cm iron plates interleaved. –Two signal planes orthogonal to each other and each having 32 pick-up strips –Total channels = 32 X 14 X 2 = 896 –Pulse height = 100 to 300mV; Rise time = < 1 ns –Pulse width = ~50ns; Rate ~ 1KHz Trigger information –Expected trigger rate is few Hz –Required Trigger logic is m X n fold, where –m = 1 to 4; no. of consecutive channels in a layer –n = 5 to 1; no. of consecutive layers with m fold in each layer –ie m x n = (1 x 5) OR (2 x 4) OR (3 x 3) OR (4 x 2) Information to be recorded on a trigger –Absolute arrival time of the trigger –Track identification (XYZ points in RPC layers) –Direction of track ( TDC information) –Miscellaneous information and calibration data Monitoring health of the detector

3. B.Satyanarayana VECC, Kolkata December 24, 20053 Readout scheme for prototype

4. B.Satyanarayana VECC, Kolkata December 24, 20054 Fast preamplifier Provided by Electronic Division, BARC Currently being used with avalanche mode operation Fixed gain (10), single channel, single polarity, with discrete components (availability issues)

5. B.Satyanarayana VECC, Kolkata December 24, 20055 Preamp hybrid Bipolar operation tested To be packaged into a hybrid (BEL) Possible to mount on the RPC pickup strips Will improve signal to noise Fabrication procedure –Circuit schematic by BARC –Layout preparation by BEL (2-3 weeks) –Pilot production by BEL and validation (1 month) –Final production (4-6 weeks)

6. B.Satyanarayana VECC, Kolkata December 24, 20056 16-channel analog front-end Based on Analog Devices’ Quad-device Fast comparator with ECL outputs Wire ORed pre-trigger outputs Production board tested with RPC strip signals Works as good as commercial units Components being procured Ready for production (2-3 months)

7. B.Satyanarayana VECC, Kolkata December 24, 20057 32-channel digital front-end

8. B.Satyanarayana VECC, Kolkata December 24, 20058 Digital front-end status Logic fused into a CPLD XC 95288 -HQ708 Code tested on a simulator and hardware using a pattern generator Jig fabricated to test the logic on RPC signals Work in progress (2 weeks) PCB layout is also in progress Production estimate about 3 months

9. B.Satyanarayana VECC, Kolkata December 24, 20059 Prototype detector trigger logic

10. B.Satyanarayana VECC, Kolkata December 24, 200510 CAMAC based trigger module FR C 60 5 Fold coincidence of consecutive F1 signals from 1 to 14 layers 2 Fold coincidence of consecutive F4 signals from 1 to 14 layers 3 Fold coincidence of consecutive F3 signals from 1 to 14 layers 4 Fold coincidence of consecutive F2 signals from 1 to 14 layers OR OR Similar coincidence logic from Y Plane signals ( 1F to 4F) OR OR Final trigger m-Fold LVDS signals (X-Plane) m-Fold LVDS signals (Y-Plane)

11. B.Satyanarayana VECC, Kolkata December 24, 200511 Trigger module status Being developed by Electronics Division, BARC Implemented using a FPGA Major part of logic coded; scalers to be done Module given for fabrication Expected to be ready in two months Testing and debugging (1 month)

12. B.Satyanarayana VECC, Kolkata December 24, 200512 CAMAC based control module Generates three sets of control and hand shake signals for selection of DFE board, readout of event data and monitoring of pickup signals in the selected board

13. B.Satyanarayana VECC, Kolkata December 24, 200513 CAMAC based readout module Four serial event data read out channels Eight monitor data inputs Serial to parallel conversion of event data Data written into FIFO buffer FIFO buffers readout through CAMAC backplane in the event routine Eight selected monitor channels translated into ECL logic signals Rates monitored through ECL input CAMAC scaler modules

14. B.Satyanarayana VECC, Kolkata December 24, 200514 Other items High voltage supplies (CAEN, SINP) Low voltage supplies (Local) Components, cables etc Commercial/available modules –TDCs –Scalers –CAMAC crates and controllers DAQ software on Linux platform

15. B.Satyanarayana VECC, Kolkata December 24, 200515 Thoughts for final detector Expertise from TIFR, BARC, SINP, VECC, IITB, IGCAR, NSC etc Industry ready and active Front-end and timing ASICs Low rates; high degree of multiplexing possible ASIC design process must begin now Comparator ASIC work by SINP Tools and training of personnel Discussion meeting at national level