1. A Method for Reducing Active and Leakage Power in Kogge-Stone Adder VLSI Design – ECE6332 Elaheh Sadredini Luonan Wang December 02, 2014

2. Motivation  Power dissipation is a critical constraint  Portable SoCs  Adders  Digital Signal Processors  Other operations like subtraction, multiplication, …

3. Carry Look-ahead Adder

4. Power Reduction with Header or Footer in CLA ● Using 8-bit CLA built with 2 4-bit CLA ● Using Ocean script to sweep through different width ● width(nm) = 50, 100, 150, 200, …, 450, 500

5. Measurement results with only footer width(nm)power(pw)delay(ps) 509.14210 10017.65203 15026.16194 20034.67188 25043.18183 30051.69179 35060.20176 40068.71174 45077.22172 50085.73170

6. Measurement results with only header width(nm)power(pw)delay(ps) 509.81210 10019.08202 15028.34196 20037.60191 25046.85187 30056.11184 35065.36181 40074.63179 45083.89176 50093.14175

7. Kogge Stone Adder (KSA) Fig 1. 16 bit KSA [1] PG Generator Dot Blocks Sum Generator

8. Leakage Power in a Dot Block P1P2G1G2Leakage Power (nw) 000041.51 0001.144.02 001.1055.53 001.1 42.77 000060.04 0001.151.78 01.1 050.66 01.1 39.77 1.100051.02 1.100 48.53 1.10 060.04 1.10 47.28 1.1 0070.72 1.1 0 62.46 1.1 061.34 1.1 50.45 Table 1. Leakage power for all different input vector in a dot block

9. Leakage power in KSA Input vectorsLeakage Power (uw) 8 bit KSA16 bit KSA All ‘0’1.894.48 All ‘1’1.964.61 101010…10101.965.97 Table 1. Leakage power for KSA

10. Worst leakage power consumption? Fig 2. Number of having P1P2G1G2=1100 for each dot block input in 8 bit KSA Count Bit index Dot block level P2=P1=1, G1=G2=0

11. Best Place for Adding Sleep Transistor  First level Dot block  Simulation results  Number of Dot block  It is more possible to save both leakage and active power  Near to PG generators

12. Multi-mode Power Gating Fig 3. Multi-mode sleep transistors: a. Normal mode, b. Cold mode, c. Park mode (intermediate power saving mode) [2]

13. Negative Clock Skew ∆ BlockDelay (ps) PG generator20 Dot block15 Sum generator20 Table 2. Delay calculation for different blocks in a 8-bit KSA ∆

14. Leakage Power Fig 4. Leakage Power for 8-bit KSA with different width in sleep transistor Leakage P (uw)Delay (ps) Without Power Gating 2.466158 With Power Gating 2.375165.23

15. Active Power Active P (uw)Delay (ps) Without Power Gating 405158 With Power Gating 263165.23 Fig 4. Active Power for 8-bit KSA with different width in sleep transistor

16. Pros and Cons  Pros  Reducing leakage power  Reducing active power  Cons  Delay into the critical path, but not that much  Area

17. Future Works  Having more than one clock skew and put more than one level into a PARK mode efficiently  Power-delay calculation for 16 bit, 32 bit KSA  Comparison with different parallel prefix adders

18. Reference [1] http://en.wikipedia.org/wiki/Kogge%E2%80%93Stone_adderhttp://en.wikipedia.org/wiki/Kogge%E2%80%93Stone_adder [2] Suhwan Kim ; Seoul Nat. Univ., Seoul ; Kosonocky, S.V. ; Knebel, D.R. ; Stawiasz, K., “A Multi- Mode Power Gating Structure for Low-Voltage Deep-Submicron CMOS ICs”, IEEE Transactions, IEEE Circuits and Systems Society, Volume:54, Issue: 7, July 2007.Suhwan KimKosonocky, S.V.Knebel, D.R.Stawiasz, K. IEEE Circuits and Systems SocietyIssue: 7 [3] Jan M. Rabaey, Anantha Chandrakasan, Borivoje Nikolic, “Digital Integrated Circuits: A Design Perspective”, Second Editon, 2003.

19. Question?

20. PG DOT SUM