1. COEN 311 Computer Organization & Software Chapter 1 Introduction and Terminology (Prof. Sofiène Tahar) Concordia University Electrical & Computer Engineering

2. Conceptual View of a Computer System P. E. Livadas, C. Ward, Computer Organization and the MC6800, Chapter 1.

3. Software Layer – Operating System View P. E. Livadas, C. Ward, Computer Organization and the MC6800, Chapter 1.

4. Inner Layers of Hardware – Physical View P. E. Livadas, C. Ward, Computer Organization and the MC6800, Chapter 1.

5. Hardware Components of a Computer System P. E. Livadas, C. Ward, Computer Organization and the MC6800, Chapter 1.

6. Opening the Box

7. Inside the Processor AMD Barcelona: 4 processor cores

8. Memory Volatile main memory – Loses instructions and data when power off Non-volatile secondary memory – Magnetic disk – Flash memory – Optical disk (CDROM, DVD)

9. Networks Communication and resource sharing Local area network (LAN): Ethernet – Within a building Wide area network (WAN): the Internet Wireless network: WiFi, Bluetooth

10. Organization of Single Bus System P. E. Livadas, C. Ward, Computer Organization and the MC6800, Chapter 1.

11. Time Sharing Process Time Printer Disk OS Routines Program User program and OS routine sharing of the processor t5t5 t4t4 t3t3 t2t2 t1t1 t0t0

12. Compilation flow

13. Software Hardware Word processor; Video game Processor: Pentium,AMD,Power PC Memory IO devices

14. Software Hardware OS Word processor; Video game Processor: Pentium,AMD,Power PC Memory IO devices Windows 2000 Unix

15. Software High Level Language Hardware OS Word processor; Video game Processor: Pentium,AMD,Power PC Memory IO devices Windows 2000 Unix, Linux C++ Java

16. Software High Level Language Machine Code Hardware OS Compiler Word processor; Video game C- compiler (high level language & processor dependent) Binary (processor dependent) Pentium, Power PC, MC68000 Processor: Pentium,AMD,Power PC Memory IO devices Windows 2000 Unix C++ Java compiler 0101011

17. Software High Level Language Assembly Language Machine Code Hardware OS Compiler Word processor; Video game C- compiler (high level language & processor dependent) Instructions (processor dependent) Pentium, Power PC, MC68000 Binary (processor dependent) Pentium, Power PC, MC68000 Processor: Pentium,AMD,Power PC Memory IO devices Windows 2000 Unix, Linux C++ Java ADD R1, R2 0101011 compiler

18. Software High Level Language Assembly Language Machine Code Hardware OS Compiler Assembler Word processor; Video game C- compiler (high level language & processor dependent) Instructions (processor dependent) Pentium, Power PC, MC68000 Binary (processor dependent) Pentium, Power PC, MC68000 Processor: Pentium,AMD,Power PC Memory IO devices Windows 2000 Unix, Linux C++ Java (processor dependent) compiler ADD R1, R2 0101011

19. Software High Level Language Assembly Language Machine Code Hardware OS Compiler Assembler Loader Word processor; Video game C- compiler (high level language & processor dependent) Binary (processor dependent) Pentium, Power PC,MC68000 Processor: Pentium,AMD,Power PC Memory IO devices Windows 2000 Unix, Linux C++ Java (processor dependent) compiler ADD R1, R2 0101011 Instructions (processor dependent) Pentium, Power PC, MC68000

20. SW Application 3 + 2 =? 5 Compilation Flow: Example

21. SW Application High Level SW Program 3 + 2 =? 5 begin var int a, b, c; a := 3; b := 2; c := a+b; end Compilation Flow: Example

22. Computer HW: Allocate variables to registers a R1 b R2 c R3 + CPU Memory Registers (R1,R2,…)

23. Computer HW: Assembly Program: Allocate variables to registers a R1 b R2 c R3 LOAD R1, 3; R1 <- 3 LOAD R2, 2; R2 <- 2 ADD R3, R1, R2; R3 <- R1+ R2 = 5 + CPU Memory Registers (R1,R2,…)

24. Computer HW: Assembly Program: Allocate variables to registers a R1 b R2 c R3 LOAD R1, 3; R1 <- 3 LOAD R2, 2; R2 <- 2 ADD R3, R1, R2; R3 <- R1+R2 = 5 1000 01 0011 Machine Program: + CPU Memory

25. Computer HW: Assembly Program: Allocate variables to registers a R1 b R2 c R3 LOAD R1, 3; R1 <- 3 LOAD R2, 2; R2 <- 2 ADD R3, R1, R2; R3 <- R1+R2 = 5 1000 10 0010 1010 11 01 10 1000 01 0011 Machine Program: + CPU Memory Registers (R1,R2,…)

26. Computer Hardware PC IR MDR Control ALU processor R0 R1 R15 n general purpose registers Memory MAR

27. Instruction Execution Fetch MAR  PC PC IR MDR Control ALU Processor R0 R1 R15 general purpose registers Memory MAR

28. Instruction Execution Fetch MAR  PC MDR  M[MAR] IR  MDR PC IR MDR Control ALU Processor R0 R1 R15 general purpose registers Memory MAR

29. Instruction Execution Execute R3 <- R1+R2 read (R1) read (R2) add write (R3) PC IR MDR Control ALU processor R0 R1 R4 general purpose registers Memory MAR R2 R3

30. ADD R3, R1, R2 MAR  PC MDR  M[MAR] IR  MDR R4  R1 + R2 PC  PC + 2 Interpret ADD Rk,Ri,Rj Increment PC Execute Decode Fetch Instruction Execution Flow

31. Next …. CPU and Memory Organization (Chapter 3)