1. Performed by: Alexander Pavlov David Domb Instructor: Mony Orbach המעבדה למערכות ספרתיות מהירות High speed digital systems laboratory הטכניון - מכון טכנולוגי לישראל הפקולטה להנדסת חשמל Technion - Israel institute of technology department of Electrical Engineering דו ” ח סיכום פרויקט ( סופי ) Subject: GPS/INS Computing System סמסטר אביב 2009 1

2. Abstract המעבדה למערכות ספרתיות מהירות High speed digital systems laboratory 2  Developed in the “Technion” and Implements the tightly coupled INS/GPS navigation unit, with the particle filter.  The algorithm stages: 0 Initialization 1 Particle Propagation 2 Particle Update & Normalization 3 State Estimation 4 Effective N calculation 5 D computation 6 Re-sampling 7 Regularization 8 Weight Re-computation

3. Solution – top design המעבדה למערכות ספרתיות מהירות High speed digital systems laboratory 3

4. Basic Architecture המעבדה למערכות ספרתיות מהירות High speed digital systems laboratory 24Bit words data bus. FIFO-Like streaming interfaces ( Request + Empty / Full ) Controlled By Start/Finished activation mechanism 4 Basic Streaming Block Basic Streaming Block Start Finished Data in Write request Full Data out Read Request Empty Control Input Path Output Path

5. Particle Propagation Unit המעבדה למערכות ספרתיות מהירות High speed digital systems laboratory 5 clock reset start finish Particle Propagation Unit X[0..439] INS[0..287] X_OUT[0..439]

6. Particle Propagation Unit המעבדה למערכות ספרתיות מהירות High speed digital systems laboratory 6 Propagation Unit 1 Propagation Unit 2 Propagation Unit 6 MUX (6 to 1) Propagation timing control

7. Single Particle Propagation Data Flow המעבדה למערכות ספרתיות מהירות High speed digital systems laboratory 7 Format inputs to 48 bits Calculate trigonometric functions Latitude sin/cos Format trigonometric function output to 48 bits R_E, R_e, R_N calculation Denominator calculation d_longitude denominator d_latitude denominator Dividers d_longitude d_lattitude R_e Particle Propagation flow control

8. Estimation Unit המעבדה למערכות ספרתיות מהירות High speed digital systems laboratory 8 clock reset New_Data_In Estimation_Ready Estimation Unit X[0..439] W[0..23] ESTIMATED_DATA [0..439]

9. Estimation Unit המעבדה למערכות ספרתיות מהירות High speed digital systems laboratory 9 W X Σ Estimated Data ×

10. Physical Implementation המעבדה למערכות ספרתיות מהירות High speed digital systems laboratory 10  Physical implementation of entire design was unsuccessful due to lack of FPGA resources.  Therefore, only 1 of the 6 parallel “propagation unit” blocks was implemented.  A design with 6 prop units will need approximately: 130K combinational ALUTs (85K available). 162K logic registers (85.2K available). 20M block memory bits (8.25M available). 4074 DSP blocks (896 available).

11. Timing Analysis המעבדה למערכות ספרתיות מהירות High speed digital systems laboratory 11  The implemented design of 1 prop unit produced: Particle LATENCY – 97 clock cycles (from “start” to “finish”) @100MHz = 1uSec Throughput of 38 clock cycles (from “finish” to “finish”) @100MHz = 380nSec  The total time with the implemented design of 1 prop unit produced was 30,000 particles in 1,140,059 100MHz clocks = 11.4mSec.

12. Accuracy Analysis המעבדה למערכות ספרתיות מהירות High speed digital systems laboratory 12  We have encountered many problems while trying to test our results: The “Generic program” for 1 FPGA did not work correctly – we were unable to control the inputs to the design. The “Generic program” for 4 FPGAs did not work as anticipated with the SW data files: o The SW data input files were arranged not according to the “bits order” agreed upon. o The program’s data output files did not reflect the output values from our design correctly.  We have made a manual accuracy check for one particle, by comparing the result as viewed with the “signal tap” tool to the SW result.  For the tested particle, we got a location result which was different from the SW result by 0.0002%

13. Project Summary המעבדה למערכות ספרתיות מהירות High speed digital systems laboratory 13  Implementation of our design - PARTIAL - due to lack of FPGA resources.  Design testing and integration - PARTIAL - due to problems with the testing environments and no cooperation from other design teams (which finished their project). In terms of possibility – it seems that it is possible to implement the “Propagation” and “Estimation” stages of the project, within the necessary timing requirements, on a better, more powerful FPGA (without changing the design)