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Renesas Electronics America Inc. © 2011 Renesas Electronics America Inc. All rights reserved. RX Bus State Controller (BSC) Ver. 1.00.

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Presentation on theme: "Renesas Electronics America Inc. © 2011 Renesas Electronics America Inc. All rights reserved. RX Bus State Controller (BSC) Ver. 1.00."— Presentation transcript:

1 Renesas Electronics America Inc. © 2011 Renesas Electronics America Inc. All rights reserved. RX Bus State Controller (BSC) Ver. 1.00

2 Course Introduction Purpose Provide details on the RX Bus State Controller (BSC) Content RX Memory Map External Chip Selects SDRAM Controller Bus Error Monitoring Learning Time 15 Minutes © 2011 Renesas Electronics America Inc. All rights reserved. 2

3 RX Memory Map On-chip resources ROM (flash) RAM Data flash Peripheral I/O registers Reserved areas External memory area Chip select areas SDRAM area CS0: a special case © 2011 Renesas Electronics America Inc. All rights reserved. 3 On-Chip resources CS Area (External address space) CS Area (External address space) SDRAM Area (External address space) SDRAM Area (External address space) On-Chip resources 0000 0000h 0100 0000h 0800 0000h 1000 0000h FFFF FFFFh

4 External Chip Selects CS0 to CS7 (CS0 is special) 16 Megabytes each Features Selectable endian mode Width: 8/16/32 bit Programmable timing Single write strobe or byte strobe mode © 2011 Renesas Electronics America Inc. All rights reserved. 4 CS7 (16 Mbytes) 0100 0000h 0300 0000h 0500 0000h 0600 0000h CS6 (16 Mbytes) CS5 (16 Mbytes) CS4 (16 Mbytes) CS3 (16 Mbytes) CS2 (16 Mbytes) CS1 (16 Mbytes) 0200 0000h 0400 0000h 0700 0000h 07FF FFFFh

5 External Bus & Control Signals © 2011 Renesas Electronics America Inc. All rights reserved. 5 D0 – D31Data bus A0 – A23Address bus CS0# – CS7#Chip selects RD#Read control WR# BC0# – BC3# Single write strobe control WR0# – WR3#Byte strobe control WAIT#External wait control OR

6 Chip Select Registers Mode Register (CSnMOD) Sets byte strobe or single write strobe mode Can enable external WAIT Enables/disables page read/write Control Register (CSnCR) Enables chip select Bus width (8/16/32) Endian Timing Registers Wait state control registers (CSnWCR1, CSnWCR2) Recovery cycle register (CSnREC) Don’t forget to configure bus clock (BCLK)! Full details in HW manual © 2011 Renesas Electronics America Inc. All rights reserved. 6

7 Chip Select Tip & Tricks CS0 is special Higher BCLK rate More wait state resolution Shorter overall wait period Endian setting is relative to processor endian setting Try to align data on natural boundaries User linker sections to group 8/16/32-bit data together Don’t cross CS boundaries in a single access © 2011 Renesas Electronics America Inc. All rights reserved. 7

8 SDRAM Controller © 2011 Renesas Electronics America Inc. All rights reserved. 8

9 SDRAM Controller Standard SDRAM interface Multiplexed row & column address (8, 9, 10, or 11 bits) x8, x16, and x32 SDRAM Auto-refresh & self-refresh Selectable CAS latency (one to three cycles) Configurable SDRAM initialization Single register to write SDRAM mode register Don’t forget the PFC! © 2011 Renesas Electronics America Inc. All rights reserved. 9 On-Chip resources CS Area (External address space) CS Area (External address space) SDRAM Area (External address space) SDRAM Area (External address space) On-Chip resources 0000 0000h 0100 0000h 0800 0000h 1000 0000h FFFF FFFFh

10 SDRAM Signals © 2011 Renesas Electronics America Inc. All rights reserved. 10 D0 – D31Data bus A0 – A23Address bus SDCS#Chip select RAS#Low address strobe CAS# Column address strobe DQM0# – DQM3#I/O data mask enables WE# Write enable SDCLK SDRAM clock CKE Clock enable

11 Bus Error Monitoring © 2011 Renesas Electronics America Inc. All rights reserved. 11

12 Bus Error Monitoring Monitors individual areas for bus errors Optionally generates interrupt on error Status regs (BERSR1, BERSR2) show who & where Illegal Address Internal addresses: Reserved areas External addresses: CSx and SDRAM area Enable with BEREN.IGAEN Monitor individual areas with CSnCNT.EXENB = 0 and SDCCR.EXENB = 0 Bus Timeout Error Applies only to CSx areas Bus access not completed (WAIT# not negated) in 768 cycles Enable with BEREN.TOEN © 2011 Renesas Electronics America Inc. All rights reserved. 12

13 Summary RX Memory Map External Chip Selects SDRAM Controller Bus Error Monitoring Thank you! © 2011 Renesas Electronics America Inc. All rights reserved. 13

14 Renesas Electronics America Inc. Thank You © 2011 Renesas Electronics America Inc. All rights reserved.


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