1. 17 December, 2010 ATLAS L1Calo upgrade meeting Meeting overview Recent hardware developments, ideas

2. 2 Upcoming dates ACES meeting (CERN, 9-11 March 2011)  Common ATLAS/CMS electronics workshop Upcoming design reviews  GOLD (beginning 2011)  CMM++ (later 2011)

3. 3 Hardware discussions Summary: recent hardware work, ideas  Control/configuration in ATCA (Ethernet, SATA...)  Data transfer formats  CPM/JEM  CMM++ (backplane)  CMM++  TP  TP readout to HLT  GOLD update (Uli)  CPM firmware upgrades (Richard) Firmware  Common development framework  Code repository, management  VHDL style guide  Collaborative firmware development  Near-term effort (what, who?):  2011 running  Upgrade (CMM++, TP...)

4. 4 Control/configuration in ATCA Email discussion in late October Some ideas discussed:  ATA over ethernet (AoE)  High performance  Low-level protocol, low overhead  Supported in Linux  Geared to block IO (512 bytes)  IP (TCP/UDP)  Widespread use  Variable-length data packets  Higher level protocol, higher overhead  Raw ethernet packets  Simple transfer protocol between hardware MAC addresses  Lower overhead than IP Physical interface probably ethernet... Set directly with geographic addr?

5. 5 Data transfer formats CPM/JEM to CMM++ (backplane) CMM++ to TP TP to HLT

6. 6 CPM/JEM to CMM++ P1P2P3P4P5P6P7P8 Threshold bits RoI 1 (8b)Threshold bits RoI 2 (8b) Fine Pos RoI 1 Fine Pos RoI 2 Fine pos RoI 3 Fine Pos RoI 4 Threshold bits RoI 3 (8b)Threshold bits RoI 4 (8b) Jet RoI 1 energy (12b)Jet RoI 2 energy (12b) Jet RoI 3 energy (12b)Jet RoI 4 energy (12b) JEM: CPM: P 1L P 1R P 2L P 2R P 3L P 3R P 4L P 4R P 5L P 5R P 6L P 6R P 7L P 7R P 8L P 8R Threshold bits RoI 1 (8b) Threshold bits RoI 2 (8b)Threshold bits RoI 3 (8b)Threshold bits RoI 4 (8b) Threshold bits RoI 5 (8b)Threshold bits RoI 6 (8b)Threshold bits RoI 8 (8b) Threshold bits RoI 9(8b)Threshold bits RoI 10 (8b) >4 RoIs / CPM probably overkill... send more information on fewer ROIs? (Richard's talk)

7. 7 CMM++ to TP Current paradigm:  Full backplane bandwidth to each CMM++ fits on12 fibers at 6.4 Gbit/s  TP receives and processes full backplane contents from all of the processor crates This is wasteful...  Backplane contents mostly empty  More fibers to TP than a single FPGA can process, forcing quadrant/merger architecture Idea: send list of non-zero ROIs, including explicit coordinates, over fewer fibers?  e.g. 4 fibers/CMM++ instead of 12  all ROIs in an event can come to a single "TP" FPGA  Multiple TP FPGAs in parallel  scalable TP

8. 8 TP to HLT HLT begins by confirming L1 trigger results For topological triggers, important to know which ROIs contributed to a given trigger bit How do we send that information?  One option: read out all ROIs from TP, adding bit fields indicating which triggers each ROI was included in.  Or: read out all ROIs from JEMs/CPMs as before, HLT reconstructs L1Calo algorithms and infers which ROIs contributed to each trigger bit.

9. 9 Firmware discussion How do we collaborate on firmware?  Common repository  HDL style guides  Strategies for collaborative development What firmware is needed soon?  2011 running  Prototype firmware for upgrade

10. 10 Other suggestions?