1. Project D02209: FPGA Bridge between High Speed Channel & External Network Mid Semester Presentation 30/05/10 Supervisor: Mony Orbach Students: Alex Blecherov Eyal Ben Dov Project Period: 2 semesters High Speed Digital Systems Lab

2. Utilizing High-speed communication between devices Narrowing the gap between High-speed LAN (via FSB) and External network (via Internet) Demand for reliable and fast communication Motivation

3. High Speed Digital Systems Lab Assuming there are several different large networks – Internal Fast Networks and External Networks (slower ones), we wish to create a mutual environment (to act as an accelerator) to provide the ability to communicate between them with high rates. General Conception

4. High Speed Digital Systems Lab Design & implementation of high speed communication bridge on Xilinx FPGA device (using SoPC) Allowing Local and External networks which operate with different protocols and rates to communicate with each other Achieving fastest transmission rate possible Explore and expertise a new FPGA device & work environment Goals

5. High Speed Digital Systems Lab Xilinx Virtex-6 ML605 FPGA Evaluation Kit ISE Design Suite Logic Edition Version 12.1 LogiCore Generator XPS ISIM / Modelsim Hardware Software Specifications

6. High Speed Digital Systems Lab Possible Solutions Local Fast Networks (up to 6 Gb/ps) Bridge: Virtex 6 ML605 FPGA External Network (TCP/IP) Bridge: Virtex 6 ML605 FPGA Local Fast Networks (up to 6 Gb/ps) Solution 1 Solution 2

7. High Speed Digital Systems Lab Chosen Solution Local Fast Networks (up to 6 Gb/ps) External Network (TCP/IP) Bridge: Virtex 6 ML605 FPGA

8. High Speed Digital Systems Lab Project Test Bench Diagram Local Fast Network (up to 6 Gb/ps) External Network (TCP/IP) Bridge: Virtex 6 ML605 FPGA

9. High Speed Digital Systems Lab Sem. A Test Bench Diagram External Network (TCP/IP) Bridge: Virtex 6 ML605 FPGA Internal Loopback

10. High Speed Digital Systems Lab Overview of the Protocols in use FSB (Internal Network) will use the Aurora protocol – IP Core. External Network will use the TCP Internet Protocol over Ethernet.

11. High Speed Digital Systems Lab Tri Mode Ethernet MAC Packet Based on IEEE Std 802.3 40-460-150026617 Number of Bytes FCSPadData Length/ Type Source Address Destination Address Start of Frame Delimiter (SFD( Preamble 64 – 1518 Bytes Preamble – Exists due to historical reasons, contains the constant pattern 0x55 [optional]. SFD - Marks the start of the frame, and must contain the value 0xD5. Destination Address - The LSB determines if the address is an individual/unicast (0) or group/multicast (1) address. It’s the first field that must always be provided.

12. High Speed Digital Systems Lab Tri Mode Ethernet MAC Packet Based on IEEE Std 802.3 40-460-150026617 Number of Bytes FCSPadData Length/ Type Source Address Destination Address Start of Frame Delimiter (SFD( Preamble 64 – 1518 Bytes Source Address – Must always be provided by the client because it’s not modified by the Ethernet MAC. Length/Type – If the decimal value of this field is 1536 or greater it’s interpreted as a Type field (Indicates if it’s a VLAN frame or PAUSE/MAC ctrl frame). Otherwise it’s interpreted as a Length field and represents the number of bytes in the following Data field.

13. High Speed Digital Systems Lab Tri Mode Ethernet MAC Packet Based on IEEE Std 802.3 40-460-150026617 Number of Bytes FCSPadData Length/ Type Source Address Destination Address Start of Frame Delimiter (SFD( Preamble 64 – 1518 Bytes Data – Varies from 0-1500 Bytes, must always be provided. Pad – Used to ensure that the frame length is at least 64 bytes in length, and required for successful CSMA/CD operation. FCS - Calculated over the destination address, source address, length/type, data, and pad fields using a 32-bit Cyclic Redundancy Check (CRC). If an incorrect FCS value is received it indicates that the received frame is bad.

14. High Speed Digital Systems Lab Internet Protocol Suite (TCP/IP) Packet – IETF – RFC 791 Version – For IPv4, this has a value of 4. Internet Header Length (IHL) - Specifies the size of the header (5-15). Differentiated Services – Type of Service - Indicates how this packet should be treated. Total Length - Defines the entire datagram size (576 - 65,535Bytes). Bit offset0-34-78-1516-1819-31 0VersionHeader length Differentiated Services Total Length 32IdentificationFlagsFragment Offset 64Time to LiveProtocolHeader Checksum 96Source Address 128Destination Address 160Options ( if Header Length > 5 ) 160 or 192+Data

15. High Speed Digital Systems Lab Internet Protocol Suite (TCP/IP) Packet – IETF – RFC 791 Identification,Flags & Fragment Offset – Used to handle received fragmented packet. Time To Live (TTL) - Indicates how many hops are allowed before the packet is discarded. Protocol - Defines the protocol used in the data portion of the IP datagram Bit offset0-34-78-1516-1819-31 0VersionHeader length Differentiated Services Total Length 32IdentificationFlagsFragment Offset 64Time to LiveProtocolHeader Checksum 96Source Address 128Destination Address 160Options ( if Header Length > 5 ) 160 or 192+Data

16. High Speed Digital Systems Lab Internet Protocol Suite (TCP/IP) Packet – IETF – RFC 791 Header Checksum - Used for error-checking of the header (calculated every hop). Source & Destination Address – An IPv4 address is a group of four octets for a total of 32 bits. Options - Additional header fields that may follow the destination address field, but usually not in use. Bit offset0-34-78-1516-1819-31 0VersionHeader length Differentiated Services Total Length 32IdentificationFlagsFragment Offset 64Time to LiveProtocolHeader Checksum 96Source Address 128Destination Address 160Options ( if Header Length > 5 ) 160 or 192+Data

17. High Speed Digital Systems Lab Overview of the Cores in use TEMAC (Tri-Mode Ethernet MAC) - The TEMAC core is designed to the IEEE 802.3 (Ethernet protocol) specification and operates in 1000Mbps, 100 Mbps, and 10 Mbps modes. We’ll use this core for the External network. Aurora - A very efficient low-latency protocol that uses the least possible amount of logic while offering excellent performance. We’ll use this core for the Internal Network (FSB).

18. High Speed Digital Systems Lab Block Diagram FSB Internal Network External Network Virtex 6 ML605 Evaluation Board RJ45 Connector GTX Transceiver Micro Blaze Aurora Protocol Ethernet SMA Connectors Protocol Translator TCP/IP - Ethernet Tri-Mode Embedded Ethernet MAC Tx FIFO Aurora IP Core Rx FIFO lwIP

19. High Speed Digital Systems Lab The Protocol Translator The protocol translator will be implemented in Xilinx SDK and will be written in C++. This unit will translate packets from Aurora protocol to TCP/IP and vice versa.

20. High Speed Digital Systems Lab Progress so far Acquiring extended knowledge of: Virtex 6 ML605 FPGA. ISE 11.5/12.1 and its tools (SDK, LogiCore Generator, XPS) In depth self-study of Ethernet & TCP/IP protocols. Creating Basic Microblaze & testing it on the board. Designing the platform’s block diagram.

21. High Speed Digital Systems Lab Detailed Time Line (Sem. A) WW 23WW 24WW 25WW 26WW 27-31Summer Creating the cores and peripherals that will be used Creating the MicroBlaze and embedding the cores Debugging the Loop back test system Performing and presenting Loop back test Exams period Preparing Part A presentation, and continue developing the bridge