1. Code Construction and FPGA Implementation of a Low-Error-Floor Multi-Rate Low-Density Parity-Check Code Decoder Lei Yang, Hui Liu, C.-J Richard Shi Transactions on Circuits and Systems 2006

2. Outline Code Design and Rates Log-BP and MSC FUs Result Conclusion Comment

3. Code Design and Rates Regular rate 5/8 code  N=149 x 8 2 = 9536  M=3 x 8 x 149 = 3576 Regular rate 7/8 code  N=17 x 24 2 = 9792  M=3 x 24 x 17 = 1224 Irregular rate 1/2 code  N=251 x 36 = 9036  M=18 x 251 = 4518

4. Code Regular code   H3 consists of randomly located permutation matrix.

5. M b x L =18 x 251 N b x L = 36 x 251 Irregular Code

7. Log-BP Check Node Computation  Variable Node Computation 

8. Min-Sum with Correction Check Node Computation  Variable Node Computation

9. Finite Precision (6:3)

10. CNU (4CU)

11. VNU

13. Architecture

14. M b x L N b x L = 36 x 251

16. Result 40Mbps @ 100MHz (24 iterations) 15Mbps @ 100MHz (60 iterations)

17. Conclusion Offer a configurable 9-kbit multi-rate LDPC decoder. (00, 01 and 10 can work at rate 1/2, 5/8 and 7/8 respectively) Archive BER 10 -5 @ 1.4dB when irregular 1/2 is operating.

18. Comment Min-Sum with Correction vs. Scaling Min- Sum Irregular Code Decoding Rate compatible Decoder

19. Comparison Ours (96x)Presented (36x) N 122889036 Rate 1/21/2,(5/8 and 7/8) Algorithm Scaling min-sumMin-sum with correction Memory 12288*(4*6+1) 307,200bit 117*512*7 + 4.5K*32 1,859,328bit F max 59.48MHz100MHz Throughput 203Mbps15Mbps (64Mbps) Gain 10 -5 at 1.610 -5 at 1.4 (block error rate 10 -7 at 1.8)