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VLSI Floorplanning and Planar Graphs prepared and Instructed by Shmuel Wimer Eng. Faculty, Bar-Ilan University July 2015VLSI Floor Planning and Planar.

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Presentation on theme: "VLSI Floorplanning and Planar Graphs prepared and Instructed by Shmuel Wimer Eng. Faculty, Bar-Ilan University July 2015VLSI Floor Planning and Planar."— Presentation transcript:

1 VLSI Floorplanning and Planar Graphs prepared and Instructed by Shmuel Wimer Eng. Faculty, Bar-Ilan University July 2015VLSI Floor Planning and Planar Graphs1

2 ENTITY test is port a: in bit; end ENTITY test; DRC LVS ERC Circuit Design Functional Design and Logic Design Physical Design Physical Verification and Signoff Fabrication System Specification Architectural Design Chip Packaging and Testing Chip Planning Placement Signal Routing Partitioning Timing Closure Clock Tree Synthesis July 2015VLSI Floor Planning and Planar Graphs2

3 GND VDD Module e I/O Pads Block Pins Block a Block b Block d Block e Floorplan Module d Module c Module b Module a Chip Planning Block c Supply Network July 2015VLSI Floor Planning and Planar Graphs3

4 July 2015VLSI Floor Planning and Planar Graphs4

5 July 2015VLSI Floor Planning and Planar Graphs5

6 Example Given: Three blocks with the following potential widths and heights Block A: w = 1, h = 4 or w = 4, h = 1 or w = 2, h = 2 Block B: w = 1, h = 2 or w = 2, h = 1 Block C: w = 1, h = 3 or w = 3, h = 1 Task: Floorplan with minimum total area enclosed A A A B B C C July 2015VLSI Floor Planning and Planar Graphs6

7 7 Example Given: Three blocks with the following potential widths and heights Block A: w = 1, h = 4 or w = 4, h = 1 or w = 2, h = 2 Block B: w = 1, h = 2 or w = 2, h = 1 Block C: w = 1, h = 3 or w = 3, h = 1 Task: Floorplan with minimum total area enclosed July 2015VLSI Floor Planning and Planar Graphs

8 Solution: Aspect ratios Block A with w = 2, h = 2; Block B with w = 2, h = 1; Block C with w = 1, h = 3 This floorplan has a global bounding box with minimum possible area (9 square units). Example Given: Three blocks with the following potential widths and heights Block A: w = 1, h = 4 or w = 4, h = 1 or w = 2, h = 2 Block B: w = 1, h = 2 or w = 2, h = 1 Block C: w = 1, h = 3 or w = 3, h = 1 Task: Floorplan with minimum total area enclosed July 2015VLSI Floor Planning and Planar Graphs8

9 Area and shape of the global bounding box – Global bounding box of a floorplan is the minimum axis-aligned rectangle that contains all floorplan blocks. – Area of the global bounding box represents the area of the top-level floorplan – Minimizing the area involves by finding the shapes of the individual blocks. July 2015VLSI Floor Planning and Planar Graphs9

10 A rectangular dissection is a division of the chip area into a set of blocks or non-overlapping rectangles. A slicing floorplan is a rectangular dissection – Obtained by repeatedly dividing each rectangle, starting with the entire chip area, into two smaller rectangles – Horizontal or vertical cut line. A slicing tree or slicing floorplan tree is a binary tree with k leaves and k – 1 internal nodes – Each leaf represents a block – Each internal node represents a horizontal or vertical cut line. July 2015VLSI Floor Planning and Planar Graphs10

11 Slicing floorplan and corresponding slicing trees b d a e c f a cb d e f H V H H V July 2015VLSI Floor Planning and Planar Graphs11

12 Non-slicing floorplans (wheels) b d a e c a b c d e July 2015VLSI Floor Planning and Planar Graphs12

13 Floorplan tree: Tree that represents a hierarchical floorplan a b c d e f g h i H H H H V W h i c d e f g a b H H Horizontal division (objects to the top and bottom) H V Vertical division (objects to the left and right) H W Wheel (4 objects cycled around a center object) July 2015VLSI Floor Planning and Planar Graphs13

14 FloorplanGraph representation Floorplan and Layout B2B2 B1B1 B3B3 B5B5 B4B4 B6B6 B 12 B9B9 B8B8 B7B7 B 10 B 11 B2B2 B1B1 B 10 B5B5 B 12 B6B6 B3B3 B9B9 B8B8 B7B7 B 11 B4B4 Vertices - vertical lines. Arcs - rectangular areas where blocks are embedded. Floorplan is represented by a planar graph. A dual graph is implied. July 2015VLSI Floor Planning and Planar Graphs14

15 Actual layout is obtained by embedding real blocks into floorplan cells. – Blocks’ adjacency relations are maintained – Blocks are not perfectly matched, thus white area (waste) results Layout width and height are obtained by assigning blocks’ dimensions to corresponding arcs. – Width and height are derived from longest paths Different block sizes yield different layout area, even if block sizes are area invariant. From Floorplan to Layout July 2015VLSI Floor Planning and Planar Graphs15

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