1. Winter-Spring 2001Codesign of Embedded Systems1 Modules in SystemC Part of HW/SW Codesign of Embedded Systems Course (CE 40-226)

2. Winter-Spring 2001Codesign of Embedded Systems2 Today programme Modules in SystemC

3. Winter-Spring 2001Codesign of Embedded Systems3 Module Advantages Building Block in Design Hierarchy Team Work Design Encapsulation Design Re-use

4. Winter-Spring 2001Codesign of Embedded Systems4 Module (cont’d) Ingredients Module Ports Module Signals Internal Data Storage Processes Module Constructors

5. Winter-Spring 2001Codesign of Embedded Systems5 Module (cont’d) Module Hierarchy Key to Implementing Complex Designs Divide and Conquer

6. Winter-Spring 2001Codesign of Embedded Systems6 Hierarchical Module Example MAC (Multiply-Accumulate) module d x + Register a c clk e f

7. Winter-Spring 2001Codesign of Embedded Systems7 Hierarchical MAC Module Example (cont’d) SC_MODULE(mac) { sc_in a,c; sc_in clk; sc_out d; sc_signal e,f; reg *r; mult *m; adder *add; SC_CTOR(mac) { r=new reg(“Register”); m=new mult(“Mult”); add=new adder(“Adder”); //Named connection r->d(f); r->q(d); m->a(a); m->b(c); m->c(e); add->a(d); add->b(e); add->c(f); } }; x + Register a c clk e f d SC_CTOR(mac) { r=new reg(“Register”); m=new mult(“Mult”); add=new adder(“Adder”); //Positional connection (*r)(f,d); (*m)(a,c,e); (*add)(d,e,f); } };

8. Winter-Spring 2001Codesign of Embedded Systems8 Hierarchical MAC Module Example (cont’d) Write down Adder and Multiplier modules in SystemC.

9. Winter-Spring 2001Codesign of Embedded Systems9 Hierarchical Module Example2 Register Module DFF clk d q

10. Winter-Spring 2001Codesign of Embedded Systems10 Hierarchical Register Module Example (cont’d) #include "dff.h" #define REG_WIDTH 10 SC_MODULE(reg) { sc_in d[REG_WIDTH]; sc_in clk; sc_out q[REG_WIDTH]; DFF *ff[REG_WIDTH]; SC_CTOR(reg) { for(int i=0; i<REG_WIDTH; i++) { ff[i] = new DFF( itoa(i,NULL,10) ); ff[i]->d(d[i]); ff[i]->q(q[i]); ff[i]->clk(clk); } };

11. Winter-Spring 2001Codesign of Embedded Systems11 Hierarchical Register Module Example (cont’d) Rewrite “Register module” in positional connection format. DFF declaration follows: SC_MODULE(DFF) { sc_in d, clk; sc_out q;... }

12. Winter-Spring 2001Codesign of Embedded Systems12 Module (cont’d) Ingredients Module Ports Module Signals Internal Data Storage Processes Module Constructors

13. Winter-Spring 2001Codesign of Embedded Systems13 Internal Data Storage: Counter Module void counter::count_up() { if (load) count_val = din; else count_val++; dout = count_val; } SC_MODULE(counter) { sc_in load; sc_in din; sc_in clock; sc_out dout; int count_val; void count_up(); SC_CTOR(counter) { SC_METHOD(count_up); sensitive_pos << clock; } };

14. Winter-Spring 2001Codesign of Embedded Systems14 Processes Implement the real function of the module Are identified to SystemC Kernel at module instantiation time Are called by SystemC Kernel whenever a change is made on their “Sensitivity List”

15. Winter-Spring 2001Codesign of Embedded Systems15 Module Constructor Identify module Processes, and their “sensitivity list” to “SystemC Kernel” Create and initialize Internal Data Structures of the module Initialize Internal Data Storage Instance name of the module is passed to the constructor at instantiation time Helps in reporting debug, error, and information messages from the module

16. Winter-Spring 2001Codesign of Embedded Systems16 What we learned today Module Concept in SystemC Module Ingredients in SystemC Hierarchical Design Using Modules

17. Winter-Spring 2001Codesign of Embedded Systems17 Complementary notes: Assignments DON’T FORGET Subscribe to ce226list@ce.sharif.edu by sending an email to majordomo@ce.sharif.edu containing subscribe ce226list in the body. Today is due date for Assignmentak 3 Take Assignment 4 Due date: Sat. Ordibehesht 1st

18. Winter-Spring 2001Codesign of Embedded Systems18 Complementary notes: Verilog Classes Today class won’t be held Synthesis Seminar Sat., Ordibehesht 8th

19. Winter-Spring 2001Codesign of Embedded Systems19 First Quiz Write a SystemC model for a synchronous up-counter with asynchronous load and clear