1. 1 CDC Readout - upgrade for Higher Luminosity - Y.Sakai (KEK) 29-Oct-2002 TRG/DAQ WS @OCU Review of Status/Plan (based on materials from S.Uno/M.Tanaka)

2. 2Introduction CDC will work at L = 10 35 → ?? x10 35 with some mod/improvement (a la S.Uno) [ small cell type CDC with R>15cm] CDC readout Electronics to be designed to work up to CDC Hardware Limit (Basic assumption) (T0 Timing device is not included here)

3. 3 Requirement: CDC Tracking: Position Resolution (  ~130um) P-id: dE/dx (  ~6% for MIPS) [ Trigger signals → not issue here (Y.Iwasaki) ] Higher Lum. Machine : higher beam current High hit rate : 100~200KHz Smaller Cell (~7mm? ← 15~18mm) Fast Gas (80~100um/ns ← <40) Max. Drift time (T max ) : ~100 ns ← 400ns Basically same as present one

4. 4 CDC Hit Rate (present) Radius = 15cm Hit rate of innermost part ＞ 100KHz chamber itself is working Other layers: ~5KHz → OK with higher beam current (>20 times higher BG)

5. 5 QT Deadtime & Efficiency QT conv. Dead time ~700ns ~200ns June-2002 Oct-2002 Innermost 2 layers QT board replaced Number of hits used in track Chamber Efficiency itself is OK with >100KHz hit rate Belle CDC

6. 6 Fast Gas : CH 4 dE/dx resolution : similar to He(50)/C 2 H 6 (50) 80~100us/ns

7. 7 CDC Readout Requirement Time Info.  T ~130um/v drift → 1.3~1.6ns (v=80~100um/ns) ~0.5 ns LSB (1 ns maybe OK), Range ~ 2T max Charge Info. Basically same as present one (except dead time) Dynamic range: >40MIPS  Q ~  PED <<  sig ~20% Linearity : < 0.5~1% Min. 10 bits (11~12 preferred) Dead Time/hit : CDC intrinsic = T max ~100ns < 500ns (10% @200KHz ， ~T max preferred) Dead Time/trig. : < 3us (10%@30KHz) Normal ! a la Tanaka-san “Pipeline” CDC hardware limit

8. 8 Possible Choices Total number of channels : ~15K (← 8.4+1.8K) Preamp/Shaper : conventional one is OK Digitizers (I) FADC only - 100MHz, 8~9bit, data compression (III) TDC + slow ADC - TMC based TDC + 10~20MHz FADC (10bit) (II) “QTC” + TDC [TDC only] - Charge integ. QT: conversion dead time - TOT type: accuracy ok for dE/dx ? thin & smaller : small cell size, less material

9. 9 (I) (II) (III) (A) (B) M.Tanaka

10. 10 10bit 200MHz FADC Performance : no problem Power : problem ~1W/ch 100MHz,8bit? Possible just do it. No R&D required Alternative solution : Analog memory with deconvolution function  ASIC  low power! Component for T & dE/dx measurements(I) R&D going on

11. 11 Component for T & dE/dx measurements(II) (K.Tauchi) A nalog: preamplifier (Gain=1.5 mV/fC, 1.5ns rise) S haping: Pole-zero cancel. (25 mV/fC, 5ns 0-paek, <2% undershoot ) D iscriminator: Baseline Restorer ( fully differencial, AC cpoupling ) Q -measurement: Time-over-Theshold, Width ~log(Q) Full range 120 fC ASDQ on Flex circuit Chip: 5.4x3.9mm2 PQFP, Rad-hard analog bipoler 8ch, 40mW, Noise ~2300e (10pF inp.cap)

12. 12 ASDQ+TDC (TMC based) System is working Enough performance for timing measurement Need detailed study for dE/dx measurement & Timing resolution<1nsec Component for T & dE/dx measurements(II) (K.Tauchi) (continued)

13. 13 FINESS User I/O board COPPER (DAQ platform)

14. 14 Conventional way –TDC  TMC core 24ch/FINESS 96ch/COPPER –ADC  10bit 20MHz HFADC 8ch/FINESS 32ch/COPPER FINESS development is on going (Trigger out to be considered) Dense implementation  ASIC(next. step) Component for T & dE/dx measurements(III)

15. 15 HFADC core (for ADC FINESS ) –~10bit –<20MHz –0.5~4.5V TMC core (for TDC FINESS) –0.2~1ns AMC core (for waveform sampler FINESS) –64 samples –Analog BW < ?? ASIC core development TADC FINESS ASIC with (ADC+TDC) (goal)

16. 16 L1 pipeline storage  T.Higuchi talk One example This will be implemented in FINESS-proto for debug of COPPER Component for COPPER I/F

17. 17 Data Size (comments) Belle CDC: ~ 2KB + 50 * cdccur0 → ~10KB @L=10 35 (~1250 hits) (~3KB=375 hits @L=3x10 33 (cdccur0=20uA) (May-2001) (now it is smaller)

18. 18Summary We are looking for person/group to work on CDC upgrade for Electronics R&D and implement (work with Tanaka-san) and for Construction / installation CDC upgrade for Higher Luminosity Readout Electronics: requirements can be satisfied with available technology R&D in progress, but still need more work

19. 19 Possibility of new TMC development project using 0.18um CMOS process Modification for our purpose may be….. Y. Arai san’s talk !!! Specification should be discussed asapAdditionally…

20. 20 Belle CDC (schematic)