1. DSP C 5000 Chapter 8 Direct Memory Access (DMA) Copyright © 2003 Texas Instruments. All rights reserved.

2. ESIEEESIEE, Slide 2 Copyright © 2003 Texas Instruments. All rights reserved. Direct Memory Access  In a real-time system, DMA is used to transfer data from peripheral/memory and memory/peripheral without burdening the CPU : DMA Input Data serial or parallel Memoryinternal/external Let’s see how the DMA performs its tasks... C55x C54x

3. Copyright © 2003 Texas Instruments. All rights reserved. ESIEEESIEE, Slide 3 Copyright © 2003 Texas Instruments. All rights reserved.   Performs data transfers without CPU intervention   Terminology - Element: basic unit of transfer (1, 2 words) - Frame: multiple elements (1-64K) - Block: multiple frames (1-256) SRC addressDST addressSOURCEDEST   Transfer dependent upon: - Source/destination address - Rotating priority between channels - Event sync (different events can be selected) - Element/Frame count - Index (can select: no modification, inc/dec by 1 and element/frame index)   Max Speed: One 16-bit word per 4 CPU cycles (all channels combined) Element 1 Element 2 Element 3 Element 4 Frame 1 Frame 2 Frame 3 Frame 4 C54x Direct Memory Access (DMA)

4. Copyright © 2003 Texas Instruments. All rights reserved. ESIEEESIEE, Slide 4 Copyright © 2003 Texas Instruments. All rights reserved. DMA Channels 0-5 SourceDestinationElem IndexFrame IndexControlStatus DE[5:0] Enable/disable channels INTSEL INTSEL Interrupt Multiplex Control DPRC Channel Priority (Hi or Low) Free Emulation Control EHPI EHPI Auxiliary Channel DMA “Resources”Peripherals Ext’l Mem SARAM DARAM DMPREC Register 14 7 5 DE[5:0]INTSELDPRC[5:0]Free 0 6138 AUTOIX 15 Only the ‘C5409, ‘10, ‘16, ‘21 and ‘41 support external DMA accesses DMA Bus Elem CountFrame Count DMA RegistersDMA Registers and Resources DMA Registers AUTOIX Extended reload mode

5. Copyright © 2003 Texas Instruments. All rights reserved. ESIEEESIEE, Slide 5 Copyright © 2003 Texas Instruments. All rights reserved. DMSFCn (Sync Event and Frame Count) 158rsvd Frame Count 071011DBLWDSYN[3:0]12   Frame Count:N-1 (N is desired # of frames)   DBLW:Double-word mode (0: 16-bit, 1: 32-bit)   DSYN:DMA sync event DSYN DMMCRn (Transfer Mode Control) 15 AUTOINIT 5 DMD 0 41011 DINDDLAXSDMSSINDSLAXS 87621   DMD:Destination Address Space (Program, Data, I/O) DMD   DIND:Destination Index (none, +, -, element/frame index) DIND   DLAXS:Internal/External Access (0/1)   DMS:Source Address Space (Program, Data, I/O) DMS   SIND:Source Index (none, +, -, element/frame index) SIND   SLAXS:Internal/External Access (0/1) DMA Registers DMA Registers DINMIMODCTMOD 1413 12

6. Copyright © 2003 Texas Instruments. All rights reserved. ESIEEESIEE, Slide 6 Copyright © 2003 Texas Instruments. All rights reserved. DMA Registers - Synchronisation Example  Index and Frame offset are 16 bits signed  Example: data sorting data sortingdata sorting

7. Copyright © 2003 Texas Instruments. All rights reserved. ESIEEESIEE, Slide 7 Copyright © 2003 Texas Instruments. All rights reserved. DMA RegistersDMA Registers – ABU Mode DMA Registers  Implements circular buffering.  Indefinite number of transfers.  Base address must be a power of two, 2 r >N, with N being the buffer size. buffer sizebuffer size  One side must be without address modification and the other can only use an indexing mode. indexing modeindexing mode McBSP DRR DMSRC1=DRR DMDST1 1E57 2089 F57B... DEAD 3000h 30FFh DMCTR1 DMSFC1

8. Copyright © 2003 Texas Instruments. All rights reserved. ESIEEESIEE, Slide 8 Copyright © 2003 Texas Instruments. All rights reserved. DMA RegistersDMA Registers – Interrupt Mode DMA Registers  DINM, IMOD and CTMOD specify interrupt mode:  DINM: no interrupt on transfer completion if 0.  CTMOD: multiframe mode if 0, ABU mode if 1.  IMOD: depend on CTMOD  Multiframe mode: interrupt occurs at end of block transfer if 0, else at the end of each frame and at the end of block transfer.  ABU mode: interrupt occurs when buffer is full if 0, else at half buffer full and at buffer full condition.

9. Copyright © 2003 Texas Instruments. All rights reserved. ESIEEESIEE, Slide 9 Copyright © 2003 Texas Instruments. All rights reserved. DMSRCn DMDSTn DMCTRn DMSFCn DMMCRn Source Address Destination Address Element Count Sync Event, Frame Count Transfer Mode Control   Writing to DMA registers is a multi-step process using sub-bank addressing DMSA DMSDN DMSDI Sub-bank Address Data Register Data Register with auto-increment   Using sub-bank addressing with auto-increment DMSRC0.set 00h STM DMSRC0,DMSA ;init DMSA to pt to DMSRC0 STM#1000h,DMSDI ;write 1000h to DMSRC0 STM#2000h,DMSDI ;write 2000h to DMDST0 …etc. MMR Regs Sub-bank Regs Writing to the DMA Registers Another example example example

10. Copyright © 2003 Texas Instruments. All rights reserved. ESIEEESIEE, Slide 10 Copyright © 2003 Texas Instruments. All rights reserved. Ch-3 Ch-2 Ch-0 High Ch-5 Ch-4 Ch-1 Low Low serviced when high: - waiting for event sync - transfers are complete   DPRC[5:0] : determines DMA bus priority between channels - (hi-1, low-0) Affects access to the 16-bit DMA bus only - Can select high or low rotating priority (per element transfer):   Priority Access to Data Buses: EHPI DMA (Hi) DMA (Lo) CPU highest lowest DMA Throughput

11. Copyright © 2003 Texas Instruments. All rights reserved. ESIEEESIEE, Slide 11 Copyright © 2003 Texas Instruments. All rights reserved. Refer to the documentation for a complete list of the DMA registers A/D McBSP DRR DMA Ch0 DMSRC0=DRR DMDST0=80h 1E57 2089 F57B... DEAD 80h 8Fh Sync event RRDY = 1 DMCTR0=15 DMSFC0=00h DMGSA=DRR DMGDA=80h DMGCR=15 DMGFR0=00h Global Reload Regs Int to CPU   Selected sync event (e.g. RRDY=1) triggers element transfer (e.g. from DRR to 80h)   Interrupt can occur at end of block or end of frame/block   DMA channel registers reloaded from reload registers at end of block transfer IF auto-init enabled.   Example shown transfers 16 values from DRR to the same memory locations every frame Example: Auto-Init and Sync Events

12. Copyright © 2003 Texas Instruments. All rights reserved. ESIEEESIEE, Slide 12 Copyright © 2003 Texas Instruments. All rights reserved. Example: Interfacing PCM3002 with DMA A/D McBSP2 DRR McBSP2 DXR D/A DMA4DMA5 PING IN PONG IN PING OUT PONG OUT PROCES- SING

13. Copyright © 2003 Texas Instruments. All rights reserved. ESIEEESIEE, Slide 13 Copyright © 2003 Texas Instruments. All rights reserved. Overview  Create a new project  Retrieve audioIO.cdb audioIO.cdb (McBSP2 configuration already done) and save it in the project directory as audioIODma.cdb  Specify buffer declaration (circular addressing constraint).  Configure DMA channels with GUI interface.  Interrupt configuration for input DMA channel

14. Copyright © 2003 Texas Instruments. All rights reserved. ESIEEESIEE, Slide 14 Copyright © 2003 Texas Instruments. All rights reserved. Create Source File  Take the file audioIODma.c and add it to the project. audioIODma.c

15. Copyright © 2003 Texas Instruments. All rights reserved. ESIEEESIEE, Slide 15 Copyright © 2003 Texas Instruments. All rights reserved. Buffer Declaration  Because of constraints on buffer address in ABU mode, the buffer must declared and handled in a special way during linking.  Add this file audioIODma.cmd audioIODma.cmd

16. Copyright © 2003 Texas Instruments. All rights reserved. ESIEEESIEE, Slide 16 Copyright © 2003 Texas Instruments. All rights reserved. DMA Configurations  Open file audioIODma.cdb and go to CSL  Add a DMA configuration named « DmaAudioRx ».

17. Copyright © 2003 Texas Instruments. All rights reserved. ESIEEESIEE, Slide 17 Copyright © 2003 Texas Instruments. All rights reserved. DMA Configuration  Select ABU for circular buffer  Interrupt on half and full buffer to implement Ping-Pong buffering  Synchronisation on receive event from AD converter through McBSP2.

18. Copyright © 2003 Texas Instruments. All rights reserved. ESIEEESIEE, Slide 18 Copyright © 2003 Texas Instruments. All rights reserved. DMA configurations source and destinatation

19. Copyright © 2003 Texas Instruments. All rights reserved. ESIEEESIEE, Slide 19 Copyright © 2003 Texas Instruments. All rights reserved. DMA Configuration  Add a new DMA configuration « DmaAudioTx ».

20. Copyright © 2003 Texas Instruments. All rights reserved. ESIEEESIEE, Slide 20 Copyright © 2003 Texas Instruments. All rights reserved. DMA configurations source and destinatation

21. Copyright © 2003 Texas Instruments. All rights reserved. ESIEEESIEE, Slide 21 Copyright © 2003 Texas Instruments. All rights reserved. DMA Settings  Select DMA4 for receive channel

22. Copyright © 2003 Texas Instruments. All rights reserved. ESIEEESIEE, Slide 22 Copyright © 2003 Texas Instruments. All rights reserved. DMA Settings  Select DMA5 for transmit channel

23. Copyright © 2003 Texas Instruments. All rights reserved. ESIEEESIEE, Slide 23 Copyright © 2003 Texas Instruments. All rights reserved. DMA Handling  Declare handle to DMA channels in source file and start transfer using CSL functions call.

24. Copyright © 2003 Texas Instruments. All rights reserved. ESIEEESIEE, Slide 24 Copyright © 2003 Texas Instruments. All rights reserved. DMA Interrupt Handling  Connect IRQ event from DMA4 to a function called RxBuffer  Unmask this interrupt and globally enable interrupts (INTM)

25. Copyright © 2003 Texas Instruments. All rights reserved. ESIEEESIEE, Slide 25 Copyright © 2003 Texas Instruments. All rights reserved. DMA Interrupt Handler  Add the DMA interrupt service routine « RxBuffer »  Build and run the application

26. Copyright © 2003 Texas Instruments. All rights reserved. ESIEEESIEE, Slide 26 Copyright © 2003 Texas Instruments. All rights reserved.   Auto-Initialization: - At end of block, DMA copies reload registers to channel registers - Reload registers can be altered at any time - Every channel can select to use auto-init and reload registers - Allows user to provide “continuous” or “repetitious” operation Other DMA Issues

27. Copyright © 2003 Texas Instruments. All rights reserved. ESIEEESIEE, Slide 27 Copyright © 2003 Texas Instruments. All rights reserved.  Performs data transfers without CPU intervention  Terminology - Element: basic unit of transfer (1, 2, or 4 bytes) - Frame: a group of 1 to 64K elements - Block: a group of 1 to 64K frames SRC addr DST addr SOURCEDEST  Transfer dependent upon: - Source/destination address - Priority (rotating priority between channels, also Ch vs. CPU) - Event sync (20 different events can be selected for ‘C5510) - Element/Frame count - Index (can select: constant, increment, element/frame index) Event syncEvent sync  Max Throughput: Two 16-bit transfers (R/W) per cycle (2 different Ch’s) Element 1 Element 2 Element 3 Element 4 Frame 1 Frame 2 Frame 3 Frame 4 ‘C55x Direct Memory Access (DMA)

28. Copyright © 2003 Texas Instruments. All rights reserved. ESIEEESIEE, Slide 28 Copyright © 2003 Texas Instruments. All rights reserved. DMA Channels 0-5 SourceDestination Elem Count Frame Count Elem Index Frame Index ControlStatus 32 32 32 16 Peripherals DMA “Ports” EMIF SARAM DARAM EHPI 16 EHPI Auxiliary Channel  DMA Channels 0-5 have access to all ports except EHPI port  EHPI Auxiliary Channel has access to all ports except Peripherals port  Each CHx has: 2 32-bit buses (R/W) + 16-bit FIFO + 8 DMA regs shown ReadBusWriteBus 16-bit FIFO 32 32 DMA Registers, Resources  EHPI share the auxiliary port with USB module

29. Copyright © 2003 Texas Instruments. All rights reserved. ESIEEESIEE, Slide 29 Copyright © 2003 Texas Instruments. All rights reserved. DMA vs EHPI  Global Control Register (DMA_GCR) DMA_GCR  If EXCL 0 all ports are connected.  If EXCL 1 ports in red are disconnected and EHPI have exclusive access to DARAM and SARAM

30. Copyright © 2003 Texas Instruments. All rights reserved. ESIEEESIEE, Slide 30 Copyright © 2003 Texas Instruments. All rights reserved. DMA throughput is affected by the combination of: Ch-3 Ch-2 Ch-0 High Ch-5 Ch-4 Ch-1 Low Low serviced when high: - waiting for event sync - transfers are complete CPU has FIXED priority over the DMA - Affects access to: RHEA, EMIF, SARAM, DARAM PRIO bits : (DMA_CCRn:6) sets priority(hi/low) for DMA channel n EHPI PRIO bit : (DMA_GCR:0) sets priority for EHPI Aux. channel - Affects access to the two 16-bit DMA buses - Can select high or low priority round robin (per element transfer) DMA_GCR 1 2 EHPI EXCL bit : (DMA_GCR:1) EHPI EXCL bit : (DMA_GCR:1)DMA_GCR - Affects access to internal/external memory - EXCL=1: EHPI accesses internal RAM only, DMA external RAM only 3 DMA Throughput

31. Copyright © 2003 Texas Instruments. All rights reserved. ESIEEESIEE, Slide 31 Copyright © 2003 Texas Instruments. All rights reserved. DMA Service Chain  Scenario  Service chain example Service chain example Service chain example

32. Copyright © 2003 Texas Instruments. All rights reserved. ESIEEESIEE, Slide 32 Copyright © 2003 Texas Instruments. All rights reserved. DMA Interrupt  Interrupts can be generated from multiple events for each channel (DMA_CICR), all interrupts are Ored :  Timeout : each resource access can be supervised thanks to a counter.  Drop : Synchronisation not serviced.  Half frame : At half of each frame.  Frame : At the end of each frame.  Last Frame : At the beginning of the last frame transfer.  Block : At the end of the block transfer.  Read DMA_CSR to determine source of interrupt

33. Copyright © 2003 Texas Instruments. All rights reserved. ESIEEESIEE, Slide 33 Copyright © 2003 Texas Instruments. All rights reserved.  Problem: - Transfer a block of pixels from SARAM to a D/A - Output via McBSP/DMA and sync transfer to D/A (ready) Src: mem_8 16-bit pixels (SARAM) DMA EXT_INT4 There’s more to set up for the DMA channel... 8910 141516 202122 23 17 11 Dest: DXR DXRMcBSP Ready D/A D DMA Channel n Source Destination Parameters Register (DMA_CSDPn) 1551713 DST BEN SRC BEN SRC PACK SRC DATA TYPE 0689DST DST PACK 1214 2 Field Description Options Answer? Field Description Options Answer? DST/SRC BEN Burst enableno burst, 4 element burst DATA TYPE Element size1, 2, or 4 bytes SRC/DST Port selectSA/DARAM, EMIF, Periph DST/SRC PACK Data packingpacked or non-packed 2 SARAM/Periph non-packed no burst Setting Up a DMA Transfer (SARAM  D/A)

34. Copyright © 2003 Texas Instruments. All rights reserved. ESIEEESIEE, Slide 34 Copyright © 2003 Texas Instruments. All rights reserved. Field Description Options Answer? Field Description Options Answer? SRC/DST AMODE Addr indexnone, +, elem indx, frm indx What other registers need to be set up?  Problem: - Transfer a block of pixels from SARAM to a D/A - Output via McBSP/DMA and sync transfer to D/A (ready) Src: mem_8 16-bit pixels (SARAM) DMA EXT_INT4 8910 141516 202122 23 17 11 Dest: DXR DXR McBSP Ready D/A D EN Ch enable0: disable, 1: enable SYNC SYNC Sync Event20 options (plus no sync) SYNC FS Frame Sync0: elem sync, 1: frame sync PRIO Priority0: low, 1: hi EXT_INT4 0 0 (or 1) DMA Channel n Control Register (DMA_CCRn) 15713 DST AMODE ENPRIO 54 FSSYNC 0689 AUTO INIT SRC AMODE 14 11 101 AUTO INIT Auto init0: none, 1: auto init 0 frm indx/ none Setting Up a DMA Transfer (SARAM  D/A)

35. Copyright © 2003 Texas Instruments. All rights reserved. ESIEEESIEE, Slide 35 Copyright © 2003 Texas Instruments. All rights reserved.DMA_CSSA_Un SRC starting BYTE Address DMA_CSSA_Ln DEST starting BYTE Address DMA_CDSA_UnDMA_CDSA_Ln DMA_CENn # of Elements DMA_CFNn # of Frames DMA_CEIn Element Index (in bytes) DMA_CFIn Frame Index (in bytes) 4326  Problem: - Transfer a block of pixels from SARAM to a D/A - Output via McBSP/DMA and sync transfer to D/A (ready) Src: mem_8 16-bit pixels (SARAM) DMA EXT_INT4 8910 141516 202122 23 17 11 Dest: DXR DXR McBSP Ready D/A D mem_8[23:16]mem_8[15:0]DXR[23:16]DXR[15:0] Note: data labels, e.g. mem_8 must be <<1 to form byte address DMA Transfer - Example

36. Copyright © 2003 Texas Instruments. All rights reserved. ESIEEESIEE, Slide 36 Copyright © 2003 Texas Instruments. All rights reserved.  Auto-Initialization: - Each channel contains “config” and “working” register sets. When auto-init is enabled, the “working registers” are reloaded from the “config” registers (which you can access via I/O memory) - Each channel contains “config” and “working” register sets. When auto-init is enabled, the “working registers” are reloaded from the “config” registers (which you can access via I/O memory) - Continuous operation: can change init/reload registers during current block transfer. Next transfer uses new values. Does not stop DMA. - Continuous operation: can change init/reload registers during current block transfer. Next transfer uses new values. Does not stop DMA. - Repetitive Operation: same init/reload registers used every time - Repetitive Operation: same init/reload registers used every time Refer to the documentation for a complete list of the DMA registers Other DMA Issues