1. Designing Combinational Systems
Chapter 5
Designing Combinational Systems

2. 5.1 ITERATIVE SYSTEMS Multiple-level circuits & iterative circuits
Chapter 5 Designing Combinational Systems
5.1 ITERATIVE SYSTEMS
Multiple-level circuits & iterative circuits
5.1.1 Delay in Combinational Logic Circuits
Full
Adder a4 b4 a3 b3 a2 b2 a1 b1 c1
cin
cout s4 s3 s2 s1
When the input to a gate changes, the output of that gate does not change instantaneously.
A small delay Δ.
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3. Chapter 5 Designing Combinational Systems
5.1 ITERATIVE SYSTEMS A B C X F
(a)
(b) 1 2 3 4 5
A block diagram of a simple circuit is shown in Figure 5.2a and the
timing diagram associated with it in Figure 5.2b.
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4. Chapter 5 Designing Combinational Systems
4 - 4
5.1 ITERATIVE SYSTEMS
Repeats the adder circuit of Example 2.31, with the delay indicated at
various points in the circuit.
The delay from the time inputs a or b change to the time that the sum is
available is 6Δ and to the time that the carry out is available is 5Δ.
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5. 5.1 ITERATIVE SYSTEMS 5.1.2 Adders
Chapter 5 Designing Combinational Systems
5.1 ITERATIVE SYSTEMS
5.1.2 Adders
A carry-ripple adder : an n-bit adder is to connect together n 1-bit adders.
The time for the output of the adder to become stable may be as large as (2n + 4)Δ.
To speed this up, several approaches have been attempted.
One approach is to implement a multi-bit adder with an SOP expression.
An example 2-bit adder.
cout = a2b2 + a1b1a2 + a1b1b2 + cinb1b2 + cinb1a2 + cina1b2 + cina1a2
s2 = a1b1a’2b’2 + a1b1a2b2 + c’ina’1a’2b2 + c’ina’1a2b’2
+ c’inb’1a’2b2 + c’inb’1a2b’2 + a’1b’1a2b’2
+ a’1b’1a’2b2 + cinb1a’2b’2 + cinb1a2b2
+ cina1a’2b’2 + cina1a2b2
s1 = c’ina’1b1 + c’ina1b’1 + cina’1b’1 + cina1b1

6. 5.1 ITERATIVE SYSTEMS Chapter 5 Designing Combinational Systems P 189
ain
aout s2 s1 1
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7. Chapter 5 Designing Combinational Systems
5.1 ITERATIVE SYSTEMS
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8. Chapter 5 Designing Combinational Systems
4 - 8
5.1 ITERATIVE SYSTEMS
Repeat this process for a 3-bit or 4-bit adder, but the algebra gets very complex and the number of terms increases drastically.
Manipulate the algebra to produce multi-level solutions with fewer large gates, but that would increase the delay.
Another problem is fan-in : a limitation on the number of inputs for a gate.
For the 2-bit adder, cout can be implemented with two-level logic.
The delay from carry-in to carry-out of every two bits is only 2Δ.
Total delay : 2Δ + 2(n/2 – 2)Δ + 3Δ = (n + 1)Δ
The carry is implemented with a two-level circuit.
The sum is a less complex multilevel circuit.

9. Chapter 5 Designing Combinational Systems
4 - 9
5.1 ITERATIVE SYSTEMS
Cascade : 4-bit adders can be cascaded for larger adders.
Carry-look-ahead adder
Each stage of the adder produces two outputs : carry generate signal (g), carry propagate signal (p)
g = ad p = a + b
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10. 5.1 ITERATIVE SYSTEMS 5.1.3 Subtractors and Adder/Subtractors
Chapter 5 Designing Combinational Systems
4 - 10
5.1 ITERATIVE SYSTEMS
5.1.3 Subtractors and Adder/Subtractors
Subtraction : Develop the truth table for a 1-bit full subtractor and cascade as many of these as are needed, producing a borrow-ripple subtractor.
Adder/Subtractor : signal line = 0 for addition & signal line = 1 for subtraction.
1 x = x’ and x = x
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11. 5.1 ITERATIVE SYSTEMS 5.1.4 Comparators
Chapter 5 Designing Combinational Systems
4 - 11
5.1 ITERATIVE SYSTEMS
5.1.4 Comparators
A common arithmetic requirement is to compare two numbers, producing an indication. (A = B or A > B) a4 b4 a3 b3 a2 b2 a1 b1
a=b
(a) Exclusive-OR
(b) Excusive-Nor
Exclusive-OR produces a 0 if a = b and a 1, otherwise.
Exclusive-NOR produces a 1 if a = b.
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12. Chapter 5 Designing Combinational Systems
4 - 12
5.1 ITERATIVE SYSTEMS =
<
> a b
Extended to any size, or 4-bit comparators can be cascaded, passing on the three signals. (greater than, less than, and equal to)
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13. Chapter 5 Designing Combinational Systems
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5.2 BINARY DECODERS
Binary decoder : when activated, selects one of several output lines, based on a coded input signal.
The input is an n-bit binary number, and there are up to 2ⁿ output lines. a b 1 2 3
The inputs are treated as a binary number, and the output selected is made active.
The output is active high, that is, the active output is 1 and the inactive ones are 0.
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14. Chapter 5 Designing Combinational Systems
4 - 14
5.2 BINARY DECODERS a b 1 2 3 a b 1 2 3
An active low output version of the decoder : one 0 corresponding to the input combination, the remaining outputs are 1.
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15. 5.2 BINARY DECODERS Most decoders also have one or more enable inputs.
Chapter 5 Designing Combinational Systems
4 - 15
5.2 BINARY DECODERS a b 1 2 3
Most decoders also have one or more enable inputs.
An input is active : the decoder behaves as described.
An input is inactive : all of the outputs of the decoder are inactive.
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16. 5.2 BINARY DECODERS Chapter 5 Designing Combinational Systems 4 - 16 a
EN’ a b 1 2 3 X a b
EN’ 1 2 3 a 1 b 2 3
EN’
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17. Chapter 5 Designing Combinational Systems
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5.2 BINARY DECODERS
Large decoder : 3-input, 8-output as well as 4-input, 16-output decoders are commercially available.
The limitation on size is based on the number of connections to the integrated circuit chip that is required.
Enables
Inputs
Outputs
EN1
EN2’
EN3’ C B A Y0 Y1 Y2 Y3 Y4 Y5 Y6 Y7 X 1 P

18. 5.2 BINARY DECODERS Example 4.1
Chapter 5 Designing Combinational Systems
4 - 18
5.2 BINARY DECODERS
Example 4.1
One of 32 devices (used decoders)
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19. 5.2 BINARY DECODERS Example 5.2
Chapter 5 Designing Combinational Systems
4 - 19
5.2 BINARY DECODERS
Example 5.2
Extra decoder is used to enable other decoders
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20. 5.2 BINARY DECODERS Example 5.3 Implementation of logic function
Chapter 5 Designing Combinational Systems
4 - 20
5.2 BINARY DECODERS
Example 5.3
Implementation of logic function
f(a, b, c) = ∑m(0, 2, 3, 7)
g(a, b, c) = ∑m(1, 4, 6, 7) P

21. 5.3 ENCODERS AND PRIORITY ENCODERS
Chapter 5 Designing Combinational Systems
4 - 21
5.3 ENCODERS AND PRIORITY ENCODERS
Binary encoder : the inverse of a binary decoder.
Binary encoder is useful when one of several devices may be signaling a
computer – encoder then produces the device number. A0 A1 A2 A3 Z0 Z1 1
Only one of the inputs can be 1, then, this table is adequate and
Z0 = A2 + A3
Z1 = A1 + A3
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22. 5.3 ENCODERS AND PRIORITY ENCODERS
Chapter 5 Designing Combinational Systems
4 - 22
5.3 ENCODERS AND PRIORITY ENCODERS
More than one input can occur at the same time,
some priority must be established. A0 A1 A2 A3 A4 A5 A6 A7 Z0 Z1 Z2 NR X 1
NR : indicates that there are no request.
NR = A’0A’1A’2A’3A’4A’5A’6A’7
Z0 = A4 + A5 + A6 + A7
Z1 = A6 + A7 + (A2 + A3)A’4A’5
Z2 = A7 + A5A’6 + A3A’4A’6 + A1A’2A’4A’6
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23. 5.3 ENCODERS AND PRIORITY ENCODERS
Chapter 5 Designing Combinational Systems
4 - 23
5.3 ENCODERS AND PRIORITY ENCODERS 1’ 2’ 3’ 4’ 5’ 6’ 7’ 8’ 9’ D’ C’ B’ A’ 1 X
The is a commercial BCD encoder, taking nine active low input lines and encoding them into four active low outputs.
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24. 5.4 MULTIPLEXERS AND DEMULTIPLEXERS
Chapter 5 Designing Combinational Systems
4 - 24
5.4 MULTIPLEXERS AND DEMULTIPLEXERS
Multiplexer : mux is basically a switch that passes one of its data inputs
through to the output, as a function of a set of select inputs.
Sets of multiplexers are used to choose among several multi-bit input numbers. w S x
out
Output, out, equals w if S = 0, and equals x is S = 1.
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25. 5.4 MULTIPLEXERS AND DEMULTIPLEXERS
Chapter 5 Designing Combinational Systems
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5.4 MULTIPLEXERS AND DEMULTIPLEXERS
Output equals input w if the select inputs (S1, S0) are 00, x if they are 01,
y if they are 10, and z if they are 11.
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26. 5.4 MULTIPLEXERS AND DEMULTIPLEXERS
Chapter 5 Designing Combinational Systems
4 - 26
5.4 MULTIPLEXERS AND DEMULTIPLEXERS
The circuit is very similar to that of the decoder, with one AND gate for
each select input combination.
Some multiplexers also have enable inputs.
out is 0 unless the enable is active.
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27. 5.4 MULTIPLEXERS AND DEMULTIPLEXERS
Chapter 5 Designing Combinational Systems
4 - 27
5.4 MULTIPLEXERS AND DEMULTIPLEXERS
Multiplexers can be used to implement logic functions.
Example 5.4
Implement the function
f(a, b) = ∑m(0, 1, 3) f b a 1 a b f 1
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28. 5.4 MULTIPLEXERS AND DEMULTIPLEXERS
Chapter 5 Designing Combinational Systems
4 - 28
5.4 MULTIPLEXERS AND DEMULTIPLEXERS
Demultiplexer : Demux is the inverse of a mux.
Demux routes a signal from one place to one of many.
It is one bit of a four-way demux, where a and b select which way the
signal, in, is directed.
The circuit is the same as for a four-way decoder with the signal in
replacing EN
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29. Chapter 5 Designing Combinational Systems
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5.5 THREE-STATE GATES
Assume that all logic levels were either 0 or 1. And encounter don’t care values.
but in any real circuit implementation, each don’t care took on either the value 0 or 1.
Never connect the output of one gate to the output of another gate, since if the two gates were producing opposite values, there would be a conflict.
Some design techniques have been used that do allow us to connect output to each other.
Three-state output gate. (or tristate output gates)
In a three-state gate, there is an enable input, shown on the side of the gate.
Input is active : the gate behaves as usual.
Control input is inactive : the output behaves as if it is not connected.
Output is typically represented by a Z.
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30. Chapter 5 Designing Combinational Systems
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5.5 THREE-STATE GATES EN a F Z 1 a f EN a f b EN
Three-state buffers with active low enables and/or outputs exist.
Three-state outputs also exist on other more complex gates.
A multiplexer using three-state gates. (without the OR gate)
The enable is the control input : f = a (EN = 0) or f = b (EN = 1)
The three-state gate is often used for signals that travel between systems.
bus : it is a set of lines over which data is transferred.
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31. 5.5 THREE-STATE GATES Example 5.5 System A B
Chapter 5 Designing Combinational Systems
5.5 THREE-STATE GATES
Example 5.5
System A B
Enable A
Enable B =
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32. 5.6 GATE ARRAYS – ROMs, PLAs, AND PALs
Chapter 5 Designing Combinational Systems
5.6 GATE ARRAYS – ROMs, PLAs, AND PALs
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33. 5.6 GATE ARRAYS – ROMs, PLAs, AND PALs
Chapter 5 Designing Combinational Systems
5.6 GATE ARRAYS – ROMs, PLAs, AND PALs
Example 5.6a
f = a’b’ + abc , g = a’b’c’ + ab + bc, h = a’b’ + c
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34. 5.6 GATE ARRAYS – ROMs, PLAs, AND PALs
Chapter 5 Designing Combinational Systems
5.6 GATE ARRAYS – ROMs, PLAs, AND PALs
Example 5.6a is rather cumbersome, particularly as the number of inputs and the number of gates increase.
Example 5.6b
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35. 5.6 GATE ARRAYS – ROMs, PLAs, AND PALs
Chapter 5 Designing Combinational Systems
5.6 GATE ARRAYS – ROMs, PLAs, AND PALs
Three common types of combinational logic arrays
Programmable Logic Array(PLA) : The user specifies all of the connection(in both the AND array and in the OR array)
Read-Only Memory(ROM) : The AND array is fixed. The user can only specify the connections to the OR gate
Programmable Array Logic(PAL) : The connections to the OR gates are specified. The user can determine the AND gate inputs
Another combinational logic array(one step further in the case of ROMs)
Erasable Programmable Read-Only Memories(EPROMs)
Many field programmable devices
make the output available in either
active high or active low form.
Exclusive-OR gate on the output
with the ability to program one of
the inputs to 0 for f and to 1 for f’
0 or 1 f
f + 0 = f
f + 1 = f’
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36. 5.6 GATE ARRAYS – ROMs, PLAs, AND PALs
Chapter 5 Designing Combinational Systems
5.6 GATE ARRAYS – ROMs, PLAs, AND PALs EN
AND Array
Out/In
Three-state output : it allows the output to be easily connected to a bus.
Three-state gate is enabled : the connection from the OR array to the output
and back as an input to the AND array is established.
Three-state gate is not enabled : the logic associated with that OR is
disconnected, the Out/In can be used as just another input to the AND array.
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37. 5.6 GATE ARRAYS – ROMs, PLAs, AND PALs
Chapter 5 Designing Combinational Systems
5.6 GATE ARRAYS – ROMs, PLAs, AND PALs
5.6.1 Designing with Read-Only Memories
Example 5.7
W(A, B, C, D) = Σm(3, 7, 8, 9, 11, 15), X(A, B, C, D) = Σm(3, 4, 5, 7, 10, 14, 15), Y(A, B, C, D) = Σm(1, 5, 7, 11, 15)
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38. 5.6 GATE ARRAYS – ROMs, PLAs, AND PALs
Chapter 5 Designing Combinational Systems
5.6 GATE ARRAYS – ROMs, PLAs, AND PALs
5.6.2 Designing with Programmable Logic Arrays
Example 5.8
W(A, B, C, D) = Σm(3, 7, 8, 9, 11, 15), X(A, B, C, D) = Σm(3, 4, 5, 7, 10, 14, 15), Y(A, B, C, D) = Σm(1, 5, 7, 11, 15)
W= AB’C’ + CD
X = A’BC’ + A’CD + ACD’ + {BCD or ABC}
Y = A’C’D + ACD + {A’BD or BCD}
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39. 5.6 GATE ARRAYS – ROMs, PLAs, AND PALs
Chapter 5 Designing Combinational Systems
5.6 GATE ARRAYS – ROMs, PLAs, AND PALs
W= AB’C’ + A’CD + ACD
X = A’BC’ + ACD’ + A’CD + BCD
Y = A’C’D + ACD + BCD
This solution only uses seven terms instead of eight or nine.
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40. 5.6 GATE ARRAYS – ROMs, PLAs, AND PALs
Chapter 5 Designing Combinational Systems
5.6 GATE ARRAYS – ROMs, PLAs, AND PALs
AB’C’ CD
A’BC’
A’CD A B C D W X Y
ACD’
BCD
A’C’D
ACD
ABC
A’BD
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41. 5.6 GATE ARRAYS – ROMs, PLAs, AND PALs
Chapter 5 Designing Combinational Systems
5.6 GATE ARRAYS – ROMs, PLAs, AND PALs
Example 5.9
To illustrate what happens when there is a term with a single literal. (in Example 3.31)
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42. 5.6 GATE ARRAYS – ROMs, PLAs, AND PALs
Chapter 5 Designing Combinational Systems
5.6 GATE ARRAYS – ROMs, PLAs, AND PALs
B’C
AB’C’
A’BD
ABD A B C D F G H BC
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43. 5.6 GATE ARRAYS – ROMs, PLAs, AND PALs
Chapter 5 Designing Combinational Systems
5.6 GATE ARRAYS – ROMs, PLAs, AND PALs
5.6.3 Designing with Programmable Array Logic
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44. 5.6 GATE ARRAYS – ROMs, PLAs, AND PALs
Chapter 5 Designing Combinational Systems
5.6 GATE ARRAYS – ROMs, PLAs, AND PALs
Example 4.10
W= AB’C’ + CD
X = A’BC’ + A’CD + ACD’ + {BCD or ABC}
Y = A’C’D + ACD + {A’BD or BCD}
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45. 5.6 GATE ARRAYS – ROMs, PLAs, AND PALs
Chapter 5 Designing Combinational Systems
5.6 GATE ARRAYS – ROMs, PLAs, AND PALs
Example 4.11
The three green terms are essential prime implicants of each function but other two are not.
f = a’b’c’ + a’c’d + b’c’d + abd’ + bcd’
g = a’b’c’ + a’c’d + b’c’d + abc + acd’
h = a’b’c’ + a’c’d + b’c’d + a’cd’ + b’cd’
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46. 5.6 GATE ARRAYS – ROMs, PLAs, AND PALs
Chapter 5 Designing Combinational Systems
5.6 GATE ARRAYS – ROMs, PLAs, AND PALs
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47. 5.7 TESTING AND SIMULATION OF COMBINATIONAL SYSTEMS
Chapter 5 Designing Combinational Systems
5.7 TESTING AND SIMULATION OF
COMBINATIONAL SYSTEMS
5.7.1 An Introduction to Verilog
Verilog and VHDL : two most widely used system a b w1 c w3 w2 x1 x2 n1 n2 n3 s
c-out
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48. 5.7 TESTING AND SIMULATION OF COMBINATIONAL SYSTEMS
Chapter 5 Designing Combinational Systems
5.7 TESTING AND SIMULATION OF
COMBINATIONAL SYSTEMS
Corresponding Verilog code (full adder)
module full_adder (c_out, s, a, b, c);
input a, b, c;
wire a, b, c;
output c_out, s;
wire c_out, s;
wire w1, w2, w3;
xor x1 (w1, a, b);
xor x2(s, w1, c);
nand n1 (w2, a, b);
nand n2 (w3, w1, c);
nand n3 (c_out, w3, w2);
endmodule

49. 5.7 TESTING AND SIMULATION OF COMBINATIONAL SYSTEMS
Chapter 5 Designing Combinational Systems
5.7 TESTING AND SIMULATION OF
COMBINATIONAL SYSTEMS
Corresponding Verilog code (4-bit adder)
module adder_4_bit( c, sum, a, b);
input a, b;
output c, sum;
wire [3:0] a, b, sum;
wire c0, c1, c2, c;
full_adder f1 (c0, sum[0], a[0], b[0], ‘b0);
full_adder f2 (c1, sum[1], a[1], b[1], c0);
full_adder f3 (c2, sum[2], a[2], b[2], c1);
full_adder f4 (c, sum[3], a[3], b[3] c2);
endmodule
A 4-bit adder can be built using the full adder as a building block.
Multibit wires are labeled with brackets.

50. 5.7 TESTING AND SIMULATION OF COMBINATIONAL SYSTEMS
Chapter 5 Designing Combinational Systems
5.7 TESTING AND SIMULATION OF
COMBINATIONAL SYSTEMS
Verilog also providers for the description of the behavior of a system,
without specifying the details of the structure.
This is often the first step in the design of a complex system, made up of a
number of modules.
The behavioral description of each module can be completed and tested.
Behavioral Verilog uses notation very similar to the C programming language.
The normal mathematics operators are available : +, -, *, /
The bitwise logical operators : ~(not), &(and), |(or), ^(exclusive or)
Two behavioral Verilog descriptions of the full adder.

51. 5.7 TESTING AND SIMULATION OF COMBINATIONAL SYSTEMS
Chapter 5 Designing Combinational Systems
5.7 TESTING AND SIMULATION OF
COMBINATIONAL SYSTEMS
module full_adder (c_out, s, a, b, c);
input a, b, c;
wire a, b, c;
output c_out, s;
reg c_out, s;
always
begin
s = a ^ b ^ c;
c_out = (a & b) | (a & c_in) | (b & c_in);
end
endmosule
(a) With logic equations.
module full_adder (c_out, s, a, b, c);
{c_out, s} = a + b + c;
endmodule
(b) With algebraic equations.

52. 5.8 LARGER EXAMPLES 5.8.1 A One-Digit Decimal Adder
Chapter 5 Designing Combinational Systems
5.8 LARGER EXAMPLES
5.8.1 A One-Digit Decimal Adder
To design an adder to add two decimal digits(plus a carry in).
This system would have nine inputs (two coded digits plus the carry in) and
five outputs (the one digit and the carry out).
Decimal addition can be performed by first doing binary addition.
A block diagram of the decimal adder, using two binary adders.
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53. 5.8 LARGER EXAMPLES A map for the carry detect circuit.
Chapter 5 Designing Combinational Systems
5.8 LARGER EXAMPLES
A map for the carry detect circuit. 00 01 11 10
s2 s1
s4 s3 1
s1 s3 c X
cout = c + s4s3 + s4s2
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54. 5.8 LARGER EXAMPLES 5.8.2 A Driver for a Seven-Segment Display
Chapter 5 Designing Combinational Systems
5.8 LARGER EXAMPLES
5.8.2 A Driver for a Seven-Segment Display
The seven-segment display : commonly used for decimal digits.
Display Driver a b c d e f g W X Y Z
Four inputs : W, X, Y, Z
Seven outputs : a, b, c, d, e, f, g
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55. 5.8 LARGER EXAMPLES Several prime implicants that can be shared.
Chapter 5 Designing Combinational Systems
5.8 LARGER EXAMPLES
Several prime implicants that can be shared.
a = W + Y + XZ + X’Z’
b = X’ + YZ + Y’Z’
c = X + Y’ + Z
d = X’Z’ + YZ’ + X’Y + XY’Z
e = X’Z’ + YZ’
f = W + X + Y’Z’
g = W + X’Y + XY’ + {XZ’ or YZ’}
The shared terms are shown in colorful.
Type
Number
Number of modules
Chip
2-in 8 2
7400
3-in 4 1
7410
4-in 3
7420
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56. Chapter 5 Designing Combinational Systems
5.8 LARGER EXAMPLES
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57. Chapter 5 Designing Combinational Systems
5.8 LARGER EXAMPLES
The minimum solutions circled. (shared prime implicants are shown circled in colorful.)
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58. Chapter 5 Designing Combinational Systems
5.8 LARGER EXAMPLES a b c d e f g
X’Y’Z’ X
WX’Y’
W’Y
W’XZ
W’Y’Z’
W’X’
W’Y’Z
X’Y’
W’X
W’Z
W’YZ’
W’X’Y
W’XY’Z
W’XY’
A row for each product term and a column for each function.
An X is placed in the column if that product term is used in the function.
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59. 5.8 LARGER EXAMPLES Minimum solution.
Chapter 5 Designing Combinational Systems
5.8 LARGER EXAMPLES
Minimum solution.
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60. Chapter 5 Designing Combinational Systems
5.8 LARGER EXAMPLES a b c d e f g
X’Y’Z’ X
WX’Y’
W’XY’Z
W’YZ
W’X’Y
W’Y’Z’
X’Y’
W’X
W’YZ’
W’XY’
This solution requires only 10 terms and thus 17 gates, a savings of 4
gates, and 54 inputs, a savings of 8 gate inputs.
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61. 5.8 LARGER EXAMPLES The corresponding equations are thus
Chapter 5 Designing Combinational Systems
5.8 LARGER EXAMPLES
The corresponding equations are thus
a = X’Y’Z’ + WX’Y’ + W’XY’Z + W’YZ + W’X’Y
b = W’YZ + W’X’Y + W’Y’Z’ + X’Y’
c = W’YZ + X’Y’ + W’X
d = X’Y’Z’ + W’XY’Z + W’X’Y + W’YZ’
e = X’Y’Z’ + W’YZ’
f = WX’Y’ + W’Y’Z’ + W’X
g = WX’Y’ + W’X’Y + W’YZ’ + W’XY’
Individually
Multiple output
Type
Chip number
Number
of modules
of module
2-in
7400 6 2 3 1
3-in
7410 10 9
4-in
7420 5 4
8-in
7430
Total 21 8 17 7
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62. 5.8 LARGER EXAMPLES Notice that these two solutions are not equal.
Chapter 5 Designing Combinational Systems
5.8 LARGER EXAMPLES
Notice that these two solutions are not equal.
First treats the don’t care in d as 0 and the don’t cares in a and f as 1’s
Second treats the don’t cares in a and d as 0’s and only the one in f as a 1.
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63. Chapter 5 Designing Combinational Systems
5.8 LARGER EXAMPLES
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