1. SEQUENCER DELAY PLD By ANTON H.C. SMITH ELECTRICAL ENGINEERING UNIVERSITY OF SOUTH CAROLINA

2. Forward Proton Detector Layout Q4 D S Q3S A1A2 P 1 UP p p Z(m) D1 Detector Bellows Roman Pot 233359 33230 57 P 2 OUT Q2 P 1 DN P 2 IN D2 Q4Q3Q2 FPD is sub-detector of DØ consisting of 9 momentum spectrometers, allowing detection of scattered anti-protons and protons and determination of momentum and scattering angle Central systems measured in DØ Detector

3. FPD ELECTRONICS Amp. Shaper MAPMT PMT FPD AFE Tester LMB FPD LM DØ LM FPD DFE FPD SEQ FPD TM L3 VRB Run I surplus Run II standard FPD custom L1 FW DFE Contr.

4. Analog Front End (AFE) Basically the interface for the SVX chips Files analog information into data stream Digitalizes fiber information for Triggering Allows algorithms that looks at hit patterns of fibers in detector to select valid tracks

5. SEQUENCER Real time manipulation of the control signal to the AFE to effect data acquisition,digitization, and readout based on the NRZ/Clock signals from the Controller.

6. SEQUENCER CONTROLLER It transforms Serial Command Link (SCL) signals into pairs of Sequencer control signals (NRZ &Clock). These signals tell the Sequencer the proper times to reset the preamps, trigger,digitize, and read out data.

7. Different Methods of Implementation Delaying the Control Signals of the AFE Delaying the NRZ signal on the Sequencer Delaying the NRZ signal going to the sequencer from the Sequencer Controller SEQUENCER CONTROLLER SEQUENCER AFE NRZ CONTROL SIGNALS

8. DELAY TIMES REQUIRED The theoretical delay times are: 321ns 575ns 636ns

9. Simple block diagram of Sequencer before modification

10. Simple block diagram of Sequencer After modification

11. Digital Logic 101 D-flip-flop OR AND NOT 4-1 multiplex 12 Bit Register

12. Block Diagram of the NEW PLD

13. Schematic of version1

14. Schematic of Communication

15. Schematic of NRZ delay Block.

16. Schematic of programmable clock delay

17. Conclusion How delays help the physics Allows the FPD data be integrated into the system Simulation results show that Min delay for Upper PLD is 188.8 ns Max delay for Upper PLD is 414.4 ns Min delay for Lower PLD is 494.8 ns Max delay for Lower PLD is 720.4 ns Resolution of about 5ns