1. Introduction or Background
NEWSDR 2015
2015 New England Workshop for Software Defined Radio
Implementation of a Full Duplex Transceiver using Xilinx Zynq SoC and ADI RFCOMMS3 Board
Benjamin Drozdenko Rahman Doost Kaushik Chowdhury Miriam Leeser
Abstract
Background
Software-defined radio (SDR) transitions the communication signal processing chain from a rigid HW platform to a user-controlled paradigm, allowing flexibility in parameter settings.
Performing the most common SDR operations in software is usually less efficient than a HW implementation.
Modern real-time bi-directional communications systems may be difficult to model using only a typical CPU.
Some components of the communication system would be more advantageously implemented using FPGA.
We design a full duplex a transceiver with split functionality between a processor and logic fabric.
We implement our design using the Xilinx Zynq ZC706 SoC and the AD-FMCOMMS3-EBZ RF transceiver.
We experiment using GNU radio and MathWorks products for building functions to interface with the radio.
IEEE a Physical (PHY) and Medium Access Control (MAC) layer frame structure with some modifications
Orthogonal Frequency Division Multiplexing (OFDM) used to carry data on multiple channels
Binary/Quadrature Phase Shift Keying (B/QPSK) modulation used to encode bits as symbols
Cyclic Prefix: prefix a symbol with a repetition of the end, eliminates intersymbol interference from previous symbol; allows linear convolution to be modeled as circular, enabling DFT
Gigabit
Ethernet
Hardware Setup
Tools Option 1
MathWorks Products: Simulink + HDL Coder
GNU Radio + Vivado
Tools Option 2
Communications System Toolbox Support Package for Xilinx Zynq-Based Radio: allows access to RFCOMMS board on Zynq using MATLAB System objects or Simulink blocks
HDL Coder Support Package for Xilinx Zynq-7000 Platform: allows generation of HDL from Simulink blocks and placement on the Zynq PL.
Embedded Coder Support Package for Xilinx Zynq-7000 Platform: allows generation of C code from MATLAB code or Simulink blocks to be built on the Zynq PS ARM.
Benefits:
Many blocks for DSP (e.g. FFT & IFFT) and communications (e.g. B/ QPSK modulation) support automatic generation of HDL & C code
Easy generation of HDL and PL image using HDL Workflow Advisor
Disadvantage:
As of R2015a, no way to model comms between PS & PL via AXI
To be added in a future release
In the meantime, must target system for either PS or PL
A PL-only Tx-Rx chain is shown at right
Not all blocks supported for HDL generation (e.g. correlation)
Data received in fixed-length packets, buffer allows accumulation of samples
Enabled subsystems allow for presence of states
In Active Search state, receiver correlates signal with preamble to find synchronization delay
In Recover Decode state, receiver performs OFDM & B/QPSK demodulation, cyclic prefix removal
OFDM blocks not supported for HDL generation, but can build using FFT/IFFT
Original HDL core only handles basic data read and write from/to ADC/DAC to/from DMA interface.
The ADC core operates at interface speed and data width and hence might cause overrun to the downstream modules.
Computationally expensive blocks, such as frame detection, can be implemented using the Vivado tools for major speed up and offloading of downstream modules.
A new interface with a different clock speed and bus width and enable/disable signals is designed.
Appropriate changes to the LIBIIO modules are applied to accommodate the low level changes. PL PS
RFCOMMS LPC
GigE
Receive Path
Transmit Path PL PS
RFCOMMS LPC
Receive Path
Transmit Path
User
Xilinx® ZYNQ™ ZC706 SoC
Processing System (PS)
Dual-Core ARM Cortex-A9 processor
Fixed architecture supports SW routines & operating systems
Programmable Logic (PL)
Equivalent to logic of an FPGA
A completely flexible canvas
Ideal for high-speed logic, arithmetic, & data flow subsystems
AXI Interconnect
Advanced Extensible Interface makes links between PL & PS
Connects peripherals in PL, incl.:
Coprocessors
Cores for interacting with external interfaces (LEDs, switches, codecs)
Additional memory elements
References
[1] IEEE Std a Part 11: Wireless LAN Medium Access. Control (MAC) and Physical Layer (PHY) specifications. URL:
[2] Analog Devices, Inc. Various (online).
“AD-FMCOMMS3-EBZ User Guide.” URL:
“What is libiio?” URL:
ADI Reference Designs HDL User Guide, URL:
EVAL-AD-FMCOMMS3-EBZ. URL:
[3] University of Strathclyde Glasgow. The Zynq Book. Embedded Processing with the ARM Cortex-A9 on the Xilinx Zynq-7000 All Programmable SoC. URL:
[4] MathWorks, Inc. Various (online).
“Guided Code Generation.” URL:
“Targeting HDL Optimized QPSK Transmitter with Analog Devices FMCOMMS2/3/4.” URL:
“Targeting HDL Optimized QPSK Receiver with Analog Devices FMCOMMS2/3/4.” URL:
[5] B. Bloessl, M. Segata, C. Sommer, and F. Dressler. An IEEE a/g/p OFDM Receiver for GNU Radio. Proceedings of the 2nd workshop on Software radio implementation forum, pp ACM, New York, NY, 2013.
[6] Xilinx, Inc. “Xilinx Zynq-7000 All Programmable SoC ZC706 Evaluation Kit.” URL:
Abstract
Introduction or Background
Goal or Aim (optional)
Method (optional)
Data or Results (includes images, figures and tables)
Conclusion
References
Acknowledgements (optional)
Analog Devices, Inc. AD-FMCOMMS3-EBZ
Designated Receiver (DRx)
Challenges
How to partition transceiver subsystem blocks between the Zynq PL & PS?
Which tools to use to generate HDL and build an image file for the Zynq SD card?
Which tools to use to generate and build C code targeted for the PS ARM?
An RF platform to software developers & system architects
Operates over a much wider tuning range, 70 MHz – 6 GHz
Works much better than the AD-FMCOMMS2-EBZ over the complete RF frequency
RX/TX RF differential-to-single- ended transformer is targeted for wider tuning range applications
Active Search
Recover Decode
Future Work
Tools Opt 1: Model OFDM & Correlation using blocks that support HDL generation
Tools Opt 2: Parametrized FPGA Blocks with proper control in the user space