1. Resets & Interrupts MTT48 3 - 80 CPU08 Core Motorola CPU08 RESETS & INTERRUPTS

3. Resets & Interrupts MTT48 3 - 82 CPU08 Core Motorola Resets & Interrupts Kinds Break Interrupt (see Break Module) Exception –Reset processing –Interrupt processing Vector Table CPU08 TOPICS

4. Resets & Interrupts MTT48 3 - 83 CPU08 Core Motorola Resets & Interrupts Resets initialize the CPU to a known state All resets are managed through the System Integration Module Reset types: –Power On – External Pin –COP – LVI –Illegal Address– Illegal Opcode Interrupts suspend normal processing so the CPU can perform some requested service Interrupt sources –IRQ1 – IRQ2 –SCI– SPI –TIM– DMA –CGM (PLL)– SWI

5. Resets & Interrupts MTT48 3 - 84 CPU08 Core Motorola Exception Processing Application ProgramException Handler RTI EXCEPTION Save Context (stacking) Find new Address (Vector Table) Load Address in PC Restore Old Context

6. Resets & Interrupts MTT48 3 - 85 CPU08 Core Motorola Exception Processing Resets and Interrupts are both CPU exceptions (to normal processing) Determining what type of handling is required, is called exception processing Exception processing is handled through discrete tasks Different for resets and interrupts –Recognition –Arbitration –Stacking –Vector fetching

7. Resets & Interrupts MTT48 3 - 86 CPU08 Core Motorola Exception Processing - Recognition- Detection of either a Reset or a pending Interrupt Resets: Recognized and acted upon immediately once asserted Interrupts: Recognized during last cycle of current instruction –Unless asserted during last cycle Will be recognized during last cycle of next instruction Acted upon after last cycle of current instruction

8. Resets & Interrupts MTT48 3 - 87 CPU08 Core Motorola Exception Processing - Arbitration - Resets: Equal and highest priority –No arbitration Interrupts: Differing priorities –Lower than resets Performed by SIM

9. Resets & Interrupts MTT48 3 - 88 CPU08 Core Motorola Exception Processing - Stacking - Saving of CPU information Resets: No stacking performed CPU state is reset Interrupts: Stacks CPU registers –PC, X, A, CCR H register is not stacked –Compatibility INTERRUPTINTERRUPT RETURNRETURN Condition Code Register Accumulator Index Register X Program Counter (H) Program Counter (L) Higher Address Lower Address

10. Resets & Interrupts MTT48 3 - 89 CPU08 Core Motorola Exception Processing - Vector Fetching - Resets: All use same vector Can determine source by examining a SIM register Interrupts: Vector depends on interrupt source 68HC708XL36 Vector Table $FFE0 - $FFE1IRQ2/Keypad $FFE2 - $FFE3SCI Transmit $FFE4 - $FFE5SCI Receive $FFE6 - $FFE7SCI Error $FFE8 - $FFE9SPI Transmit $FFEA - $FFEBSPI Receive $FFEC - $FFEDTIM Overflow $FFEE - $FFEFTIM Channel 3 $FFF0 - $FFF1TIM Channel 2 $FFF2 - $FFF3TIM Channel 1 $FFF4 - $FFF5TIM Channel 0 $FFF6 - $FFF7DMA $FFF8 - $FFF9PLL $FFFA - $FFFBIRQ1 $FFFC - $FFFDSWI $FFFE - $FFFFRESET

11. Resets & Interrupts MTT48 3 - 90 CPU08 Core Motorola Reset Processing RESET Fetch Reset Vector from $FFFE-$FFFF UserMonitor Fetch Reset Vector from $FEFE-$FEFF Mode ? Set I-bit in CCR to prevent interrupts Reset internal registers. Includes CPU and sub module registers. See individual registers for reset states. Load Stack Pointer with $00FF Load Program Counter with contents of Reset Vector Begin execution

12. Resets & Interrupts MTT48 3 - 91 CPU08 Core Motorola Interrupt Processing Note that the H Index register is not saved on the stack. The I-bit is cleared by the unstacking of the Condition Code Register. INTERRUPT Last cycle of current instruction Complete next instruction fetch (Redundant) Stack Program Counter Stack X Index register Stack Accumulator Stack Condition Code register Fetch vector Load Program Counter with vector contents Set I bit to prevent interrupts Begin execution. Service the interrupt. Complete next instruction fetch (Unused) Unstack Condition Code register Unstack Accumulator Unstack X Index register Unstack Program Counter Fetch next instruction Interrupt Pending? Yes No 1 1 First cycle of next instruction

13. Resets & Interrupts MTT48 3 - 92 CPU08 Core Motorola Masking Enabling/Disabling of exception processing. Resets: Can NOT be masked. Interrupts: Can be masked I bit enables/disables all interrupt processing Local masks in peripherals for masking individual interrupts

14. Resets & Interrupts MTT48 3 - 93 CPU08 Core Motorola DESIGN EXERCISE PART2 Write a code sequence Executes at RESET Calls your RAM initialization –How do you make sure this code executes at RESET? Given: ORG$6E00 STARTUP......; Program startup and initialization ORG$FFE0; Vector Table FCBIRQ2SRV; IRQ2 Service Routine FCBSCIXMIT; SCI Transmit Service Routine FCBSCIRECV; SCI Receive Service Routine FCB?????;Reset Handler