1. High Speed Digital Systems Lab Spring/Winter 2010 Project definition Instructor: Rolf Hilgendorf Students: Elad Mor, Ilya Zavolsky Integration of an A/D Converter Into The Sub-Nyquist Xampling System

2. 2 Topics Sub-Nyquist Xampling system Overview Sub-Nyquist Xampling system Overview The main goal The main goal Review of the Texas Instruments ADS6423 Review of the Texas Instruments ADS6423 LVDS Background LVDS Background I/O scheme I/O scheme A/D chip diagram and output interface A/D chip diagram and output interface FPGA receiver block diagram FPGA receiver block diagram A/D control interface A/D control interface Time table of semester A Time table of semester A Integration of an A/D into Xampling System

3. Sub-Nyquist Xampling system Overview 3 Integration of an A/D into Xampling System Our goal is to integrate a sub-system that would convert the incoming analog samples to digital signals. Then they will be processed and reconstructed in the sub-Nyquist Sampling system. Our goal is to integrate a sub-system that would convert the incoming analog samples to digital signals. Then they will be processed and reconstructed in the sub-Nyquist Sampling system. For this purpose we shall use the TI ADS6423 Evaluation module. For this purpose we shall use the TI ADS6423 Evaluation module.

4. 4 The main goal To configure and integrate the ADS6423 A/D card to the sub-Nyquist experimental Xampling system. To configure and integrate the ADS6423 A/D card to the sub-Nyquist experimental Xampling system. The A/D converter will receive wide spectrum signal by four channels and will transmit serial high speed digital outputs (LVDS). The A/D converter will receive wide spectrum signal by four channels and will transmit serial high speed digital outputs (LVDS). To design and implement an I/O adapter card which will assign the correct pins between the A/D and the Gidel card To design and implement an I/O adapter card which will assign the correct pins between the A/D and the Gidel card To create a control environment to set-up and monitor the A/D which will be integrated onto an ALTERA FPGA and monitored from a PC. To create a control environment to set-up and monitor the A/D which will be integrated onto an ALTERA FPGA and monitored from a PC. To create an initial and a permanent testing environment for the module. To create an initial and a permanent testing environment for the module. Integration of an A/D into Xampling System

5. Review of Texas Instruments ADS6423 EVM 5 Integration of an A/D into Xampling System The ADS6423 is a high performance 12 bit, 105/80 MSPS, quad channel A-D converter. The ADS6423 is a high performance 12 bit, 105/80 MSPS, quad channel A-D converter. It is configured to accept 4 single ended input sources (Through COAX cables). It is configured to accept 4 single ended input sources (Through COAX cables). The ADC outputs are serialized data, a bit clock and a frame clock which are brought to a high density connector. The ADC outputs are serialized data, a bit clock and a frame clock which are brought to a high density connector.

6. LVDS Background LVDS – Low Voltage Differential Signaling, is a signaling method which uses a pair of inductors to transmit two different voltages that are compared at the receiver. LVDS – Low Voltage Differential Signaling, is a signaling method which uses a pair of inductors to transmit two different voltages that are compared at the receiver. 6 Integration of an A/D into Xampling System A typical LVDS driver – receiver pair is shown above; nominal 3.5 mA current source is located in the driver. Since the input impedance of the receiver is high, the entire current effectively flows through the 100Ω termination resulting in a 350 mV voltage across the receiver inputs. The receiver threshold is guaranteed to be 100 mV or less, and this sensitivity is maintained over a wide common mode from 0V to 2.4V. A typical LVDS driver – receiver pair is shown above; nominal 3.5 mA current source is located in the driver. Since the input impedance of the receiver is high, the entire current effectively flows through the 100Ω termination resulting in a 350 mV voltage across the receiver inputs. The receiver threshold is guaranteed to be 100 mV or less, and this sensitivity is maintained over a wide common mode from 0V to 2.4V.

7. 7 Integration of an A/D into Xampling System The 350 mV typical signal swing of LVDS consumes only a small amount of power and therefore LVDS is a very efficient technology, delivering performance at data rates up to 3.125 Gbps. The 350 mV typical signal swing of LVDS consumes only a small amount of power and therefore LVDS is a very efficient technology, delivering performance at data rates up to 3.125 Gbps. The simple termination, low power, and low noise generation generally make LVDS the technology of choice for data rates from tens of Mbps up to 3 Gbps and beyond. The simple termination, low power, and low noise generation generally make LVDS the technology of choice for data rates from tens of Mbps up to 3 Gbps and beyond.

8. I/O scheme 8 Integration of an A/D into Xampling System a) 4 incoming channels of analog input signal, 60 MHz each, 1 Volt peak-to-peak. b) 8 LVDS Pairs that enters the Gidel Card after being assigned inside the pin adapter (390 Mbit/sec). We also transmit a Frame clock out of the A/D device. c) Clock and control signals that are generated on the Gidel ProcStarIII. d) 4 channels x12 bit of de-serialized output which will be sent to the expand sequence module. e) Pin Adapter card which we are going to design and implement. It’s purpose is to connect the correct pins on the PSDB connection on the Gidel card onto the ADS6423. (Meet Gidel Personnel to inquire about this solution and determine if LVDS+Non LVDS combination is possible on same PSDB slot.)

9. A/D chip block diagram 9 Integration of an A/D into Xampling System

10. FPGA receiver block diagram 10 Integration of an A/D into Xampling System

11. The Altera Stratix III Differential signals Receiver 11 Integration of an A/D into Xampling System The Stratix III device has dedicated circuitry to receive high-speed differential signals. The Stratix III device has dedicated circuitry to receive high-speed differential signals. The receiver has a differential buffer, PLL, DPA block, synchronization FIFO buffer, data realignment block, and a deserializer. The receiver has a differential buffer, PLL, DPA block, synchronization FIFO buffer, data realignment block, and a deserializer.

12. A/D Card and ALTERA LVDS common-mode Since the ALTERA Differential Voltage receiver top speed is 500 Mbit/sec, the A/D most appropriate interface option is the 2-wire, SDR bit clock, 12x serialization. This option will produce an output serial data rate of 390 Mbit/sec. Since the ALTERA Differential Voltage receiver top speed is 500 Mbit/sec, the A/D most appropriate interface option is the 2-wire, SDR bit clock, 12x serialization. This option will produce an output serial data rate of 390 Mbit/sec. 12 Integration of an A/D into Xampling System

13. A/D digital ouput Interface 13 Integration of an A/D into Xampling System The Most suitable option is 2-Wire, 1 × frame clock, 12 × serialization, with SDR bit clock, byte wise/bit wise/word wise. The Most suitable option is 2-Wire, 1 × frame clock, 12 × serialization, with SDR bit clock, byte wise/bit wise/word wise.

14. A/D control interface 14 Integration of an A/D into Xampling System ADS6423 offers flexibility with several programmable features. ADS6423 offers flexibility with several programmable features. At first, we intend to use both the serial interface and parallel controls (combination of jumpers and serial interface), due to its simplicity. At first, we intend to use both the serial interface and parallel controls (combination of jumpers and serial interface), due to its simplicity. As the project evolves, we will upgrade to serial interface programming only. As the project evolves, we will upgrade to serial interface programming only. Serial interface programming mode are used to access the internal registers of ADC. Serial interface programming mode are used to access the internal registers of ADC.

15. 15 Time table (Semester A) Task \ Week 1234567891011121314 Exploring the problem 8/3 Definition presentation 22/4 Explore Altera LVDS receiver Acquire tool knowledge* Define A/D configuration Midterm presentation Define an initial test env. Design an adapter card Design of the A/D Controller Design of LVDS Receiver logic Integration of the system Form a debug strategy 30-01 Integration of an A/D into Xampling System

16. 16 Questions / Answers Thank you! Integration of an A/D into Xampling System

17. (Task List for Semester B) Forming a debug strategy Forming a debug strategy To Define and Implement a permanent test environment. To Define and Implement a permanent test environment. To Build a PC control interface using PROC- wizard. To Build a PC control interface using PROC- wizard. To create a configuration and operation protocol for the sub-Nyquist sampling system user. To create a configuration and operation protocol for the sub-Nyquist sampling system user. 17 Integration of an A/D into Xampling System