1. Chapter 3: Combinational Functions and Circuits 3-5 to 3-7: Decoders
CS 151: Digital Design
Chapter 3: Combinational Functions and Circuits
3-5 to 3-7: Decoders

2. Overview Part II Functions and functional blocks
Rudimentary logic functions
Decoding
Encoding
Selecting
Implementing Combinational Functions Using:
Decoders and OR gates
Multiplexers (and inverter)
CS 151

3. Functions and Functional Blocks
The functions considered are those found to be very useful in design
Corresponding to each of the functions is a combinational circuit implementation called a functional block.
In the past, many functional blocks were implemented as SSI, MSI, and LSI circuits.
Today, they are often simply parts within a VLSI circuits.
CS 151

4. Rudimentary Logic Functions
Functions of a single variable X
Can be used on the inputs to functional blocks to implement other than the block’s intended function 1 F =
(a) V CC
or V DD
(b) X
(c)
(d)
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5. Multiple-bit Rudimentary Functions
Multi-bit Examples:
A wide line is used to represent a bus which is a vector signal
In (b) of the example, F = (F3, F2, F1, F0) is a bus.
The bus can be split into individual bits as shown in (b)
Sets of bits can be split from the bus as shown in (c) for bits 2 and 1 of F.
The sets of bits need not be continuous as shown in (d) for bits 3, 1, and 0 of F. A F A 3 2 3 1 F 1 2 4 4
2:1
F(2:1) 2 F F F 1 1
(c) A F A
(a)
(b) 3
3,1:0 4
F(3), F(1:0) F
(d)
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6. Enabling Function
Enabling permits an input signal to pass through to an output
Disabling blocks an input signal from passing through to an output, replacing it with a fixed value
The value on the output when it is disable can be Hi-Z (as for three-state buffers and transmission gates), 0 , or 1
When disabled, 0 output
When disabled, 1 output
See Enabling App in text
CS 151

7. Decoding
A binary code of n bits is capable of representing 2n elements.
Decoding - the conversion of an n-bit coded input to a maximum of 2n unique outputs.
Circuits that perform decoding are called decoders.
Here, functional blocks for decoding are
called n-to-m line decoders, where m ≤ 2n, and
generate 2n (or fewer) minterms for the n input variables
n-to-m Line Decoder
. . .
m outputs
m <= 2n
n inputs
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8. Decoder Examples
1-to-2-Line Decoder
2-to-4-Line Decoder = =
Note that the 2-4-line made up of 2 1-to line decoders and 4 AND gates.
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9. Decoder Examples
3-to-8-Line Decoder: example: Binary-to-octal conversion.
D0 = m0 = A2’A1’A0’
D1= m1 = A2’A1’A0
…etc
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10. Decoder with Enable
In general, attach m-enabling circuits to the outputs
See truth table below for function
Note use of X’s to denote both 0 and 1
Combination containing two X’s represent four binary combinations EN A 1 EN A A D D D D 1 1 2 3 A X X D 1 1 1 1 1 1 1 1 D 1 1 1 1 1 D
(a) 2 D 3
(b)
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11. Decoder Expansion - Example 1
Decoders with enable inputs can be connected together to form a larger decoder circuit.
Enable
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12. Decoder Expansion - Example 2
Construct a 5-to-32-line decoder using four 3-8-line decoders with enable inputs and a 2-to-4-line decoder. A0 A1 A2
3-8-line Decoder E
D0 – D7
D8 – D15
D16 – D23
D24 – D31
2-4-line Decoder A3 A4
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13. Decoders can implement any function!
Since any function can be represented as a some-of-minterms, a decoder can be used to generate the minterms, and an external OR gate to form their sum.
A combinational circuit with n inputs and m outputs can be implemented with an n-to-2n line decoder and m OR gates. X Y Z C S 1
Number of Ones = 3
Number of Ones = 0
Number of Ones = 1
Number of Ones = 2
S(X,Y,Z)=  m (1,2,4,7)
C(X,Y,Z)=  m (3,5,6,7)
CS 151