1. 1 Expanded Modes, Bus, External Memory Today: First Hour: Expanded Modes, Bus, Timing –Section 4.1-4.7.2 of Huang’s Textbook –In-class Activity #1 Second Hour: Interfacing external memory to 6811 Section 4.7.3 of Huang’s Textbook –In-class Activity #2

2. 2 Single chip mode: a mode in which the 68HC11 functions without external address and data buses. The 68HC11 has 5 I/O ports (A, B, C, D, and E) to use in this mode. Expanded mode: a mode in which the 68HC11 has the capability to access a 64KB address space. Port B is used as the upper address signals (A15-A8) Port C is used as time-multiplexed address/data bus (A7/D7-A0/D0). Only three I/O ports are available for direct use. Choosing modes: MODB, MODA pins (look up PRG!) (1,0) => single chip; (1,1) => Expanded 6811Operation Modes

3. 3 ROM-8KB RAM-256 bytes EEPROM-512 bytes PORT A PULSE ACCUMULATOR PERIODIC INTERRUPT COP WATCHDOG PAI OC2 OC3 OC4 OC5 O C 1 IC1 IC2 IC3 PA7 PA6 PA5 PA4 PA3 PA2 PA1 PA0 PE7 PE6 PE5 PE4 PE3 PE2 PE1 PE0 PORT E V REFH V REFL A/D CONVERTER DATA DIRECTION PORT D SS SCK MOSI MISO SPI TxD RxD SCI PD5 PD4 PD3 PD2 PD1 PD0 M68HC11 CPU ADDRESS DATA BUS INTERRUPTS RESET XIRQ IRQ (V PPBULK ) HANDSHAKE I/O DATA DIRECTION C PORT CPORT B PARALLEL I/O SINGLE CHIP P B 7 P B 6 P B 5 P B 4 P B 3 P B 2 P B 1 P B 0 P C 7 P C 6 P C 5 P C 4 P C 3 P C 2 P C 1 P C 0 S T R A S T R B A 1 5 A 1 4 A 1 3 A 1 2 A 1 1 A 1 0 A 9 A 8 A D 7 A D 6 A D 5 A D 4 A D 3 A D 2 A D 1 A D 0 R/W AS EXPAND OSCILLATOR XTAL EXTAL E MODA LIR MODB (V STBY ) V DD V SS MODE SELECT POWER Expanded Mode

4. 4 E R/W AS AD7-AD0 68HC11 PC7-PC0 A15-A8 PB7-PB0 MODB MODA Bus Expanded Mode 1 1 Other pins not shown

5. 5 A real signal has nonzero rise and fall times 90% V DD 10% V DD 1 0 t rise t fall Timing Conventions Recap Single-signal waveform 1 0 1 0 Multiple-signal waveform

6. 6 Unknown signals (when they are changing) representation (a) Single signal unknown (b) multiple signals Unknown signals Timing Conventions Recap

7. 7 A floating signal is represented by a level half way between logic high and low. Signal floating (a) Single signal Signals floating (b) multiple signals Floating signals Timing Conventions Recap

8. 8 Crystal & E-clock E XTAL Crystal clock: 8 MHz => One cycle = 125 ns 125 ns E clock: 2 MHz => One cycle = 500 ns 500 ns

9. 9 E R/W A15-A8 A7/D7-A0/D0LO-ADDRDATA AS XTAL Bus Timing Diagram HI ADDR Observe that AD lines active as address only for 1/2 E cycle Most external memory devices need address lines active for 1E cycle AS line to the rescue, combined with external address latch!

10. 10 CLK OE A B C D E F G H QA QB QC QD QE QF QG QH 373 11 1 3 4 7 8 13 14 17 18 2 5 6 9 12 15 16 19 74373 Octal Transparent Latch with 3-State Outputs Stores an 8 bit number Positive edge triggered /OE is active LO output enable Determines when register contents are visible at the outputs /OE is active LO output enable Determines when register contents are visible at the outputs LE 11 LE: Latch Enable. High => latch is transparent to data inputs

11. 11 Latching the Address E R/W AS AD7-AD0 68HC11 PC7-PC0 A15-A8 PB7-PB0 MODB MODA Bus 1 1 Other pins not shown D0-D7 Q0-Q7 A0-A7 373 LE Address A0-A7 latched on the falling edge of AS OE 0

12. 12 Latching (contd) Latching allows A7-A0 to be available for the second half of the E-clock cycle at the output of the latch E AS 250 ns 125 ns A0-A7 latched at falling AS edge A7/D7-A0/D0LO-ADDRDATA

13. 13 Do Activity #1 Now

14. 14 Memory mapping external memory => can access external memory using normal instructions and memory addresses. Similar to I/O memory mapping Address space assignment -Use only unallocated memory space -Allocated in units of 2 n KB (n is an integer) Allocated space for the 68HC11A8 $0000-$00FF:SRAM $1000-$103F:I/O registers $B600-B7FF:EEPROM $E000-$FFFF:ROM Memory Mapping

15. 15 Memory Mapping Example Consider an external 13-bit memory chip => 8KB Divide 64 KB space into eight 8KB blocks. Block number Address range 0123456701234567 $0000-$1FFF $2000-$3FFF $4000-$5FFF $6000-$7FFF $8000-$9FFF $A000-$BFFF $C000-$DFFF $E000-$FFFF Map external memory to: $4000-$5FFF

16. 16 Address Decoding First four bits of memory map: 0100 or 0101 Partial decoding: A[15-13] = 010 O0 O1 O2 O3 O4 O5 O6 O7 E1 E2 E3 A2 A1 A0 74LS138 Address decoder design A15 A14 A13 External Memory E 010 Why is E connected to E3 ?

17. 17 Decoding (contd) 74LS138: E3: active high enable => Decoding done when E clock is high I.e at second-half of E-clock cycle Goal: Enable (chip select) external memory with the output (O2) of decode at this time I.e. at second-half of E-clock cycle E Decoded values available

18. 18 Two chip enable signals: CS1 is active low CS2 is active high. WE: write enable (active low) OE: output enable (active low) 8KB SRAM HM6264A

19. 19 Putting it together A2 A1 A0 E3 E2E1 PB7/A15 PB6/A14 PB5/A13 E R/W PB4/A12 - PB0/A8 AS AD7-AD0 LE D7-D0 O7-O0 OE I/O8 - I/O1 WE CS1 CS2 V DD O2 A12-A0 OE HM6264A 74F138 68HC11 74F373 74LS00 74LS04

20. 20 E R/W A15-A8 A7/D7-A0/D0LO-ADDRDATA AS XTAL Revisit: Bus Timing Diagram HI ADDR Second half of E-cycle

21. 21 Putting it together (contd) During second-half of E-cycle –CS1 asserted (from O2) –E =1 during this time => R/W’ passed to WE’ »Recall: (X.1)’ = X’ {NAND gate} »In this case, X = (R/W’)’{NOT gate} –Latch output holds A0-A7 –AD0-AD7 connected to I/O lines of SRAM »Data sent back to port C if it is a READ »Data sent from port C if it is a WRITE E Second half of E-cycle

22. 22 Do Activity #2 Now Due: End of Class Today. RETAIN THE LAST PAGE(S) (#3 onwards)!! For Next Class: Read Chapter 4 of Huang Review all material, identify your problem areas, and Bring your questions! Next week’s studio: Catch up with experiments. Summarize reading of Chapter 4, Chapter 5 (sections 5.1-5.4), and Chapter 6 (6.1 – 6.7)