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Status of the Beetle front-end chip carrier for SRS Lorne Levinson Weizmann Institute of Science Rehovot, Israel L. Levinson, Weizmann Institute, Nov.

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Presentation on theme: "Status of the Beetle front-end chip carrier for SRS Lorne Levinson Weizmann Institute of Science Rehovot, Israel L. Levinson, Weizmann Institute, Nov."— Presentation transcript:

1 Status of the Beetle front-end chip carrier for SRS Lorne Levinson Weizmann Institute of Science Rehovot, Israel L. Levinson, Weizmann Institute, Nov. 2011Beetle Carrier for SRS1

2 Beetle chip A pipelined readout chip built for LHCb inner tracker – Max-Planck-Institute for Nuclear Physics, Heidelberg, Germany – NIKHEF / Free University Amsterdam, The Netherlands – Physics Institute, University of Heidelberg, Heidelberg, Germany – University of Oxford, Oxford, United Kingdom Rad Hard: > 130MRad, TMR for SEUs 128 channel analogue or binary (fixed pulse or Time-Over-Threshold) 40MHz, 160 sample pipeline and “an integrated multi-event buffer of 16 stages” 3.6 microsec readout time for analog mode, 900nsec for binary mode Discriminator outputs for trigger: – Groups of 4 adjacent channels are OR’ed together and output as 32 LVDS signals – discriminator pulse or time-over-threshold L. Levinson, Weizmann Institute, Nov. 2011Beetle Carrier for SRS2

3 Carrier specs Card format is the same as the AVP carrier for SRS. – Same 2  128 pin front end signal connector – uses the micro-HDMI connector to the SRS system Two cards (256 channels) can be read out via one HDMI connector – Flat cable connects master to optional slave card – No slave option for binary output, i.e. 128 channels per HDMI cable On-board FPGA generates a trigger signal sent back on HDMI cable to SRS – FPGA not needed if trigger generation is not wanted Trigger output calculated from 32 trigger outputs of the Beetle chip – Actel flash FPGA can be reprogrammed via JTAG – FPGA is not rad hard, perhaps rad tol to 30krad. L. Levinson, Weizmann Institute, Nov. 2011Beetle Carrier for SRS3

4 Trigger examples L. Levinson, Weizmann Institute, Sept 2011 1.Simple OR of all channels 2.Track in a 4 layer tower: – Input ribbon cable can be split into four ribbons, each going to 128/4 = 32 channels in each of 4 layers – Adjacent groups of 4 channels are OR’d by Beetle and sent out i.e. 8 towers – For each of the 8 towers find 3-out-of-4 coincidence (or 2-out-of-4, 4-out-of-4, etc.) – Trigger output is OR of the 8 tower coincidences Beetle Carrier for SRS4

5 Production status Like the AVP carrier, this board requires direct wire bonding from the chip pads on the die to the PCB. PCB traces and vias are smaller than most PCB houses can make, … and smaller than the AVP. Design work complete. Production files about to be sent to PCB fabricator and assembly house for checking and price quotes. – same companies as for the AVP carrier: Eltos, Hybrid SA Will do a small pre-series to test the board followed by a production run Tell us if you are interested in using this chip/carrier so we can plan the order. Issue: limited supply of CERN PLL25 chips: – we will check if we can use the FPGA instead L. Levinson, Weizmann Institute, Nov. 2011Beetle Carrier for SRS5

6 Beetle carrier for SRS L. Levinson, Weizmann Institute, Nov 2011Beetle Carrier for SRS6


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