1. GEM 型放射線イメージング装 置用フロントエンド LSI の開発 2007 年 12 月 15 日 4 th MPGD 研究会＠大阪市大 房安貴弘 1 ＊ 、佐野哲 2 、田中義人 1 、浜垣秀樹 2 1 長崎総合科学大学 2 東京大学原子核科学研究センター

2. Motivation GEM を用いた X 線イメージングや中性子線イ メージングのため、専用のフロントエンド LSI を 開発。 X 線の場合。 考古学のフィールドワークや医療用など 中性子線の場合。 エンジン中の液体の動的観察など

3. Pixel Readout Method ① Pixels on LSI NIM A535 (2004) 477 ② Multiple LSI’s Max Size = 2cm x 2cm 2 x 2 LSI’s are maximum because of bonding pads → Max size = 4cm x 4cm ③ PCB Bd Difficulty in wiring. → Min. pixel size = about 1mm 2 ④ Use TFT process for LCD Difficulty in availability

4. Readout Circuit For Still X-ray Imaging Incident signal on GEM sheet Trigger Clock Analog Out CH1 2 3 4 5 ・・・・・・・・・・・ Still Imaging. We want to obtain information per particle.

5. Readout Circuit For Motion Imaging by Neutron Imaging rate = about 100rps x 10frames = 1 ０００ fps → Need fast readout 1ms 積分の後、読出し、放電。 放電直後のベースライン電位も測定。 Frame Signal

6. Prototype Strategy w/o peak-hold circuit and shaper because of integration mode for neutron imaging. w/o output buffer. Trigger is given by user. Use TSMC 0.25  m 1P5M n-well process. VDD=2.5V.

7. Schematic of Channel MUX 1pF Discharge switch Compensating dummy switch Folded-Cascode OPamp Test Pulse Input Pixel Charge Input Shift Register Switch Control Over-Voltage Protection W/L=8  m/4  m from the previous channel to the next channel

8. Schematic of OP amp Standard Folded-Cascode OP amp DC Open loop gain64.2dB gain band width 63.1MH z phase margin77.4° Common-mode gain-16.7dB Common-mode rejection ratio 80.4dB PSRR+70.1dB PSRR-84.1dB output impedance414kΩ slew rate 148V/u s settling time (1%) 26.1ns OP amp feature obtained by simulation

9. Layout Design 5mm 2.5mm 1ch circuit OPamp Capacitors MUX Shift Register switch 230um Process: TSMC 0.25  m 1P5M n-well Chip size: 5mm×2.5mm The design has been submitted for fabrication. The chip has been obtained in Nov/2007.

10. Layout Simulation Parasitic RC’s are extracted. Analog Output of the Chip (i.e. MUX out) Droop of the Capacitor 7mV droop during a frame period, of which 4mV is due to the discharge switch. Rise time = 50ns. Setting time = 160ns (0.1%).

11. Layout Simulation Total power dissipation of the chip : 75mW Crosstalk between neighboring channels : 0.01% Clock migration to the analog out : 10mV pp

12. PCB Design

13. PCB Circuits ＬＳＩからの出力領域 0.75-1.75V (Vref=0.75V) ADC(AD7825) の conversion 領域 0-2.5V ADC : 8bit 1.5V 0.75-1.75V 0.1-2.4V 1k1.3k 3.3p 1.5k 1k

14. PCB Fabricated with ASIC

15. Summary and Future Frontend ASIC for GEM imaging was fabricated using TSMC 0.25  m process. Layout simulation has been done. System test using GEM chamber will be performed @ CNS. Single chip test will be performed @ Nagasaki. Integrate with pipelined ADC?