1. An Abstract Model of De- synchronous Circuit Design and Its Area Optimization Jin Gang University of Manchester

2. Overview Motivation Design flow Abstract model － Control Graph Timed Petri-net model for Control Path Performance Evaluation Area Optimization Conclusion

3. Motivation Asynchronous Circuit –Benefit Low power Better EMC Modularity –Drawback Difficult to design

4. Motivation De-synchronous Circuit –Benefit Benefit from Asynchronous Design within synchronous design tools –Drawback Not the original asynchronous design method May introduce some area overhead into circuit

5. Design Flow Datapath design is the same as synchronous counterpart More concern need to give to the control path

6. Design Flow 1. Split each flip-flop into a master-slave latch pair. 2. Generate the matched delay unit for each combinational logic path. 3. Implement the local controller corresponding to each latch.

7. Control Graph An abstract model for control path Use a directed graph to represent the control path Purpose of this model –Evaluate the performance of the circuit –Optimize the circuit

8. Control Graph

10. Timed Petri-net model for control path A Timed Petri-net model for control path can be derived from control graph

11. Performance Evaluation Use the average cycle time to evaluate the performance of the de-synchronous circuit The performance evaluation is a linear programming problem

12. Area Optimization Multi local controllers can be combined to a single local controller Condition –Only the local controllers with same polarity can be combined –This combination can preserve the equality of the circuit

13. Area Optimization

14. This optimization problem is NP-hard The optimizing procedure need be directed by the performance evaluation function, which can grantee the performance of the circuit This optimization is a trade-off between the area and the benefit of asynchronous circuit

15. Area Optimization Θ is the a threshold defined to control the maximal number of the latches can driven by a single local controller After the optimization, the fan-in and fan- out of the control path will be changed, so the area also will be changed according it

16. Results Θ=2 OriginalOptimized CircuitVertexEdgeC-elementVertexEdgeC-element s276104462 s298288355163822 s344309363164024 s349309363164024 s3861242306126 s42032152120144428 s5101242306126 s52642165123227755 s14481242306126

17. Results Θ=3 OriginalOptimized CircuitVertexEdgeC-elementVertexEdgeC-element s276104462 s298288355122513 s344309363122513 s349309363122513 s386124230462 s42032152120123018 s510124230462 s52642165123144834 s14481242306126

18. The change of average fan-in and fan-out OriginalOptimized CircuitAverage fan-in/outAverage fan-in/out(Θ=2)Average fan-in/out(Θ=3) s27 2.673.00 s298 3.964.154.42 s344 4.104.385.42 s349 4.104.385.42 s386 4.504.004.50 s420 5.754.755.17 s510 4.504.004.50 s526 4.935.416.43 s1448 4.504.00

19. Conclusion Compatible with synchronous design method Can reduce the area overhead of the control path Can preserve the performance of the circuit Will lose some benefit of asynchronous circuit

20. Finish Thanks for your attention