1. DDRIII BASED GENERAL PURPOSE FIFO ON VIRTEX-6 FPGA ML605 BOARD PART B PRESENTATION STUDENTS: OLEG KORENEV EUGENE REZNIK SUPERVISOR: ROLF HILGENDORF 1 Semester: spring 2013

2. CONTENT 1.Project overview 2.Specifications 3.Part B goals 4.Memory on ml605 5.AXI4 6.Part A overview 7.Part B overview Design Performance 2

3. PROJECT OVERVIEW Design and implementation of General Purpose FIFO IP core which allows usage of external memory (DDR3) as FIFO storage on Xilinx FPGA device Design and implement generic IP core of FIFO Design and implement GUI generator of IP core on PC Create sample design with implemented IP core 3

4. SPECIFICATIONS Hardware Xilinx Virtex-6 ML605 FPGA Evaluation Kit DDR III memory Ethernet interface PC with Ethernet interface Software ISE Design Suite Logic Edition Version 14.3 Modelsim Wireshark Winpcap library 4

5. OUR GOALS Create design with configurable in/out word size depth Develop software generator of GP FIFO IP core Achieve best performance Minimize usage of FPGA resources Make our world a better place 5

6. MEMORY ON ML605 DDR3 memory Capacity: 512MB Max theoretical bandwidth: 800MT/s*64bit = 48.8Gb/sec Xilinx provides us with DDR3 controller which has AXI Memory Mapped interface AXI bus data width up to 1024 bit 256 bit for max memory performance, assuming bus works with 200Mhz 6

7. 4AXI Xilinx provides us with AXI4 Memory Mapped bus, which is a standard bus used in modern ARM SoC. Features Separate Address/Control and Data Phases burst-based transactions with only start address issued separate read and write data channels 7

8. CONTROLLER Native Fifo Interface MEMORY TO FIFO FIFOFIFO FIFO TO MEMORY FIFOFIFO GENERAL PURPOSE FIFO AXI4 Interface

9. GENERAL PURPOSE FIFO INTERFACE GP FIFO Native FIFOAXI4

10. PART A OVERVIEW GENERAL PURPOSE FIFO Interface GP FIFO has native FIFO interface In Word size is 32 bit Out Word size is 32 bit Utilizes DDR3 memory through AXI interconnect 32 bit wide Depth is limited only by available RAM memory on DDR3 Same clock domain for IN and OUT Internal architecture Internal FIFO-To-Memory controller Internal Memory-To-FIFO controller Internal Bypass controller Arbitration between GP FIFOs is managed by AXI interconnect 10

11. MAC Module EXAMPLE DESIGN BLOCK DIAGRAM 11 MEMORY CONTROLLER AXI4 BUS (INTERCONNECT) General Purpose Fifo Example Design MAC Controller HOST General Purpose Fifo

12. Interface Utilizes Ethernet MAC level of communication Software has simple and intuitive interface Software handles all the data transmission in between host and GP FIFO Internal architecture MAC module GP FIFO Simple example of a logic which uses GP FIFO Example design of part A is dedicated to verify GP FIFO core under maximum performance condition. In part B we tested different configurations (variable word size). 12 PART A OVERVIEW EXAMPLE DESIGN

13. OUR GOALS PART B Generalize our GP FIFO Develop software generator for GP FIFO IP core Write detailed manual for IP core and for it’s generator Develop simple design to test performance Simulate and test all the possible configurations and their exceptional case Make possible optimizations 13

14. PART B OVERVIEW GENERAL PURPOSE FIFO Interface GP FIFO has native FIFO interface GP FIFO has configurable internal word size: 64, 128, 256 bit In/Out word size can be 8, 16, 32, 64, 128, 256 bit Maximum ratio of internal word size to In/Out is x8 Depth is defined by two addresses: start and end. Those two addresses define continuous region of memory which is used for GP FIFO and thus its depth. Same clock domain for reader and writer Internal architecture Input and output buffers has fixed depth of 128 words to maximize performance 14

15. PART B OVERVIEW SOFTWARE GENERATOR FOR GP FIFO IP CORE Developed in Java Available GP FIFO core configuration parameters Name Start address of utilized RAM memory End address of utilized RAM memory In word size Out word size Internal word size: 64b, 128b, 256b Maximum ratio of internal word size to In/Out is x8 15

16. PART B OVERVIEW SOFTWARE GENERATOR FOR GP FIFO IP CORE 16

17. PART B OVERVIEW SOFTWARE GENERATOR FOR GP FIFO IP CORE Provides user with a convenient way of GP FIFO parameterization Prepares simulation of generated GP FIFO 17

18. MAC Module EXAMPLE DESIGN BLOCK DIAGRAM 18 MEMORY CONTROLLER AXI4 BUS (INTERCONNECT) General Purpose Fifo Example Design MAC Controller HOST

19. Example design of part B is dedicated to measure maximum performance of GP FIFO core with different configurations. Interface with host Utilizes Ethernet MAC level of communication Software developed in Part A Internal architecture MAC module GP FIFO Simple logic Simultaneously writes/reads GP FIFO. Sends word count to Host every second. 19 PART B OVERVIEW EXAMPLE DESIGN

20. PART B OVERVIEW PERFORMANCE OF DIFFERENT CONFIGURATIONS We defined three stages in exploring performance of GP FIFO under different configurations. GP FIFO of size 64Mb In/Out is symmetric (variable) Example Design and GP FIFO are running with 200MHz clock Performance dependence on depth of In/Out buffer Internal word size 64 bit In/Out buffer depth is variable Performance dependence on internal word size Internal word size: 128, 256 bit is variable In/Out buffer depth is 128 words 20

21. PART B OVERVIEW PERFORMANCE DEPENDENCE ON IN/OUT BUFFER DEPTH 21

22. PART B OVERVIEW PERFORMANCE DEPENDENCE ON IN/OUT BUFFER DEPTH 22

23. PART B OVERVIEW PERFORMANCE DEPENDENCE ON IN/OUT BUFFER DEPTH 23

24. PART B OVERVIEW PERFORMANCE DEPENDENCE ON INTERNAL WORD SIZE 24

25. PART B OVERVIEW PERFORMANCE DEPENDENCE ON INTERNAL WORD SIZE 25

26. PART B OVERVIEW PERFORMANCE DEPENDENCE ON INTERNAL WORD SIZE 26

27. PART B OVERVIEW PERFORMANCE DEPENDENCE ON INTERNAL WORD SIZE 27

28. PART B OVERVIEW PERFORMANCE OF DIFFERENT CONFIGURATIONS Performance dependence on depth of In/Out buffer Deeper buffer results in higher average speed only when in/out word size is greater/equals internal word size Performance dependence on internal word size Increasing internal word size provides significant speedup Optimal internal word size is twice as in/out word size Experiment shows that speed of GP FIFO in real design correlates well with simulated values Conclusion Changing buffer depth can hide some latency in case of not optimal internal word size, does not provide significant speedup to the system Optimal internal word size is x2 max{in, out} word size 28

29. PROJECT OVERVIEW Our design meets the requirements of the project. GP FIFO is fast limited only by interconnect bus available bandwidth GP FIFO has configurable depth and word size GP FIFO is simple, utilizes small amount of resources on the board GP FIFO gives you another easy way to pass big chunks of data from one module to another. GP FIFO core generator provides an easy way to configure the core. Our example design provides you with efficient communication in between a host and the board. After one and a half year of hard work we finally reached all sgoals of the project 29