1. Numerical signal processing for LVDT reading based on rad tol components Salvatore Danzeca Ph.D. STUDENT (CERN EN/STI/ECE ) Students’ coffee meeting 1/3/2012 1

2. Radiation field in the tunnel of LHC The radiation field in the LHC is mainly due to: Beam collision in the experiment points (ATLAS, LHCb, CMS, ALICE) Beam collision with residual gas in the pipe Beam collision with collimator, beam dump, etc.. Not Shielded Areas 2 Shielded Areas

3. Effect of radiation on the electronic devices Cumulative effects Single Event Effects (SEE) Total Ionizing Dose (TID) Potentially all components Displacement damage Bipolar technologies Optocouplers Optical sources Optical detectors (photodiodes) Permanent SEEs SEL CMOS technologies SEB Power MOSFETs, BJT and diodes SEGR Power MOSFETs Static SEEs SEU Digital ICs Transient SEEs Combinational logic Operational amplifiers 3

4. Conditioning and acquisition system architecture 4

5. Objectives / Targets Acquisition and processing in REAL TIME with a sampling rate of 250 kSps Uncertainty on position 1.0 μm Position survey frequency 100 Hz Possibility of multiple sensor readings in parallel Numeric Resolution of 0.5 μm Being radiation tolerant up to 100 Gy of Total Ionizing Dose; low number of SEU for a given fluence of 10 11 pp/cm 2 5

6. LVDT and position reading Sine Fit Ratiometric 6

7. Acquisition and processing: CPU vs FPGA 7

8. Is it possible to go faster? 8 SNR = 60 dB 1.0 μm TARGET

9. Numerical algorithm FPGA implies the fixed point algorithm Why? Floating point would not assure the required performance in terms of calculation time and area occupancy Fixed point is simpler; thus less prone to SEU effects 9

10. Fixed Point Algorithm 16 bit 41 bit 82 bit42 bit43 bit 10

11. Low and Medium resolution algorithm ImplementationArea OccupancyClock Frequency Low resolutionCore Cells:35197 of 24576 (143%)2.3 MHz - 434.570 ns Medium resolution Core Cells:41780 of 24576 (170%)1.7 MHz -588.235 ns Low res Medium res 16 bit 41 bit 18 bit 16 bit 32 bit 36 bit 11

12. CORDIC Ac As A1-A2 A1+A2 Vectoring Mode Circular Rotation “Linear” Rotation Vectoring Mode 12

13. Cordic = High resolution algorithm 41 bit 42 bit ImplementationArea AllocationClock Frequency High resolution (A3PE1000)Core Cells: 11881 of 24576 (48%)25.6 MHz-39.031 ns High resolution with TMRCore Cells: 14572 of 24576 (59%)24.7 MHz-40.427 ns High resolution on A3PE3000Core Cells: 11465 of 75264 (15%) 23.9 MHz- 41.796 1 CLR CLK D Q Triple Modular Redudancy 13

14. How to evaluate the algorithm Simulation – Emulation of the secondary voltages in Matlab – Emulation of a 0.5 μm movement – Comparison of the Low- Medium- High- resolution algorithms(all fixed point) VS floating point algorithm Experimental data from LHC collimator – Analysis on a 5 μm movement at different absolute positions – Comparison of the Low- Medium- High- resolution algorithms(all fixed point) VS floating point algorithm 14

15. Simulation results 0,5 μm with Low resolution algorithm 15

16. 16 Simulation results 0,5 μm with Medium resolution algorithm

17. 17 Simulation results 0,5 μm with High resolution algorithm

18. Experimental Results Low resolution Medium resolution Low Res Max error [µm] Medium Res Max error [µm] High Resolution with 32 bit Max error [µm] Position 9730µm7,74990,78789,57E-05 Position 9715µm8,48100,55881,20E-04 Position 9710µm4,13101,02751,99E-04 Position 9715µm7,28700,81736,94E-05 Total max error8,48101,02751,99E-04 18

19. Radiation Test Results Paul Scherrer Institut 230 MeV Proton Beam Cross Section Proton Beam DUT [1] NanoFIP Large Scale Radiation Tests, 2012, E. Gousiou 19 [2] nanoFIP Preliminary Radiation Tests - Test Report, 2011, E. Gousiou [3] ADC MAX11046 test 03.06.2011 at PSI Institute –Test Report, 2011, G. Spiezia, P. Perronard, S. Danzeca

20. Conclusions High resolution algorithm – CORDIC based – complies to the specifications of 0,5 μm of numeric resolution Possibility of using a single FPGA (A3PE1000) for readings of 2 LVDTs in parallel Application of a redundancy scheme for mitigate the effects of radiation ADC and FPGA can be considered radiation tolerant in an environment characterized by a TID of 100 Gy and a fluence of 1e11cm -2 20

21. BACKUP SLIDES DAC PCM RADIATION TEST SETUP AND RESULTS SEU SIMULATION ON LVDT VOLTAGE ACQUISITION. WHAT HAPPENS TO THE POSITION? 21

22. DAC PCM1702 Radiation test setup 22

23. PSI Beam conditions 23 Taken in consideration only for the current drift because of some problem at the anti-latch up circuit Taken in consideration for the SEU after removing the anti-latch up board

24. OUTPUT ANALYSIS ON RUN 50 24 NO SEU

25. Current supply (+5V) analysis in the runs 45-48 25 NO DRIFT

26. 26 Current supply (-5V) analysis in the runs 45-48 DRIFT START AT 100 Gy OUT OF SPEC ~ 200 Gy

27. SEU SIMULATION ON LVDT OUTPUT 27 If we want to simulate an SEU two parameter have to be considered: 1.SEU POSITION IN THE 16 BIT ADC REGISTER 2.SEU POSITION IN THE ACQUIRED SINE WAVE Wait until SEU on bit = 8 to see the SEU effects on the most significant BIT Play ANIMATION

28. Maximum Error due to SEU on position evaluation 28