1. DR. SIMING LIU SPRING 2016 COMPUTER SCIENCE AND ENGINEERING UNIVERSITY OF NEVADA, RENO Session 7, 8 Instruction Set Architecture

2. The MIPS Instruction Set Used as the example throughout the book Stanford MIPS commercialized by MIPS Technologies (www.mips.com) Large share of embedded core market Applications in consumer electronics, network/storage equipment, cameras, printers, … Typical of many modern ISAs See MIPS Reference Data tear-out card, and Appendixes B and E

3. Stored Program Concept Instructions are bits Programs are stored in memory  To be read or written just like Data CPU Memory I/O Fallout 4 MS Word C compiler Payroll data Source code in C Memory for data, programs, compilers, editors, etc.

4. MIPS Instruction Set Architecture Instruction Categories  Load/Store  Arithmetic  Jump and Branch  Floating Point  coprocessor  Memory Management  Special R0 - R31 PC Hi Lo OPrsrtrdsafunctOPrsrtimmediateOPJump target 3 Instruction types, 32 bits wide R format I format J format

5. MIPS (RISC) Design Principles Simplicity favors regularity  Fixed size instructions  Small number of instruction formats  opcode always the first bits Smaller is faster  Limited instruction set  Limited number of registers in register file  Limited number of addressing modes Make the common case fast  Arithmetic operands from the register file (load-store machine)  Allow instructions to contain immediate operands Good design demands good compromises  Three instruction formats

6. Chapter 2 — Instructions: Language of the Computer — 6 Arithmetic Operations Add and subtract, three operands  Two sources and one destination add a, b, c # a gets b + c All arithmetic operations have this form Design Principle 1: Simplicity favors regularity  Regularity makes implementation simpler  Simplicity enables higher performance at lower cost §2.2 Operations of the Computer Hardware

7. Chapter 2 — Instructions: Language of the Computer — 7 Arithmetic Example C code: f = (g + h) - (i + j); Compiled “MIPS code”: add t0, g, h # temp t0 = g + h add t1, i, j # temp t1 = i + j sub f, t0, t1 # f = t0 - t1

8. MIPS Arithmetic Instructions MIPS assembly language arithmetic statement add $t0, $s1, $s2 sub $t0, $s1, $s2 Each arithmetic instruction performs one operation Each specifies exactly three operands that are all contained in the datapath’s register file ( $t0,$s1,$s2) destination <- source1 op source2 Instruction Format (R format) 01718800x22

9. Chapter 2 — Instructions: Language of the Computer — 9 MIPS Arithmetic Instruction Fields  op: operation code (opcode)  rs: first source register number  rt: second source register number  rd: destination register number  shamt: shift amount (00000 for now)  funct: function code (extends opcode) oprsrtrdshamtfunct 6 bits 5 bits MIPS fields are given names to make them easier to refer to

10. Chapter 2 — Instructions: Language of the Computer — 10 Register Operands Arithmetic instructions use register operands MIPS has a 32 × 32-bit register file  Use for frequently accessed data  Numbered 0 to 31  32-bit data called a “word” Assembler names  $t0, $t1, …, $t9 for temporary values  $s0, $s1, …, $s7 for saved variables Design Principle 2: Smaller is faster  c.f. main memory: millions of locations §2.3 Operands of the Computer Hardware

11. Chapter 2 — Instructions: Language of the Computer — 11 Register Operand Example C code: f = (g + h) - (i + j);  f, …, j in $s0, …, $s4 Compiled MIPS code: add $t0, $s1, $s2 add $t1, $s3, $s4 sub $s0, $t0, $t1

12. Chapter 2 — Instructions: Language of the Computer — 12 Memory Operands Main memory used for composite data  Arrays, structures, dynamic data To apply arithmetic operations  Load values from memory into registers  Store result from register to memory Memory is byte addressed  Each address identifies an 8-bit byte Words are aligned in memory  Address must be a multiple of 4

13. MIPS Memory Access Instructions MIPS has two basic data transfer instructions for accessing memory The data is loaded into (lw) or stored from (sw) a register in the register file – a 5 bit address lw $t0, 4($s3) #load word from memory sw $t0, 8($s3) #store word to memory

14. Chapter 2 — Instructions: Language of the Computer — 14 Memory Operand Example 1 C code: g = h + A[8];  g in $s1, h in $s2, base address of A in $s3 Compiled MIPS code:  Index 8 requires offset of 32  4 bytes per word lw $t0, 32($s3) # load word add $s1, $s2, $t0 offset base register

15. Chapter 2 — Instructions: Language of the Computer — 15 Memory Operand Example 2 C code: A[12] = h + A[8];  h in $s2, base address of A in $s3 Compiled MIPS code:  Index 8 requires offset of 32 lw $t0, 32($s3) # load word add $t0, $s2, $t0 sw $t0, 48($s3) # store word

16. Chapter 2 — Instructions: Language of the Computer — 16 Registers vs. Memory Registers are faster to access than memory Operating on memory data requires loads and stores  More instructions to be executed Compiler must use registers for variables as much as possible  Only spill to memory for less frequently used variables  Register optimization is important!

17. Machine Language – Load Instruction Load/Store Instruction Format (I format): lw $t0, 24 ($s3) 3519824 10 6 bits5 bits 16 bits 0x00000000 0x00000004 0x00000008 0x0000000c 0x12004094 0xffffffff $s3 24 10 + $s3 = …0001 1000 + …1001 0100 …1010 1100 = 0x120040ac Memory (24)$s3 0x120040ac

18. Byte Addresses Since 8-bit bytes are so useful, most architectures address individual bytes in memory  Alignment restriction – the memory address of a word must be on natural word boundaries (a multiple of 4 in MIPS-32) Big Endian: left most byte is word address  IBM 360/370, Motorola 68k, MIPS, SPARC, HP PA Little Endian: right most byte is word address  Intel 80x86, DEC Vax, DEC Alpha

19. Word Alignment Struct A{ char c; char d; int i; } Struct B{ char c; int i; char d; } int main(){ cout<<sizeof(A); cout<<sizeof(B); } 8 12 ( gcc-4.3.4 )

20. Chapter 2 — Instructions: Language of the Computer — 20 Byte/Halfword Operations Could use bitwise operations MIPS byte/halfword load/store  String processing is a common case lb rt, offset(rs) lh rt, offset(rs)  Sign extend to 32 bits in rt lbu rt, offset(rs) lhu rt, offset(rs)  Zero extend to 32 bits in rt sb rt, offset(rs) sh rt, offset(rs)  Store just rightmost byte/halfword

21. Chapter 2 — Instructions: Language of the Computer — 21 Immediate Operands Constant data specified in an instruction addi $s3, $s3, 4 No subtract immediate instruction  Just use a negative constant addi $s2, $s1, -1 Design Principle 3: Make the common case fast  Small constants are common (50% of MIPS arithmetic instructions in SPEC2006 use constants!)  Immediate operand avoids a load instruction

22. Chapter 2 — Instructions: Language of the Computer — 22 The Constant Zero MIPS register 0 ($zero) is the constant 0  Cannot be overwritten Useful for common operations  E.g., move between registers add $t2, $s1, $zero

23. Aside: MIPS Register Convention NameRegister Number UsagePreserve on call? $zero 0Constant 0 (hardware)n.a. $at 1Reserved for assemblern.a. $v0-$v1 2-3Returned valuesNo $a0-$a3 4-7ArgumentsNo $t0-$t7 8-15TemporariesNo $s0-$s7 16-23Saved valuesYes $t8-$t9 24-25TemporariesNo $k0-$k1 26-27Reserved for OSn.a. $gp 28Global pointerYes $sp 29Stack pointerYes $fp 30Frame pointerYes $ra 31Return address (hardware)Yes