1. March 3rd, 2008 EE235 Nanofabrication, University of California Berkeley Hybrid Approach of Top Down and Bottom Up to Achieve Nanofabrication of Carbon Nanotube Devices Maggie Zhang

2. March 3rd, 2008 EE235 Nanofabrication, University of California Berkeley A Dielectrophoretic Method for High Yield Deposition of Suspended, Individual Carbon Nanotubes with four-Point Electrode Contact Manufacture four-point contacted suspended, individual multiwalled carbon nanotubes by dielectrophoresis –DEP (dielectrophoresis) force is exerted on a dielectric particle when it is subjected to a non-uniform electric field Bulk Carbon Nanotube Self Assembly (Chinese U of HK) Avoid time-consuming in-situ manipulation: AFM etc. –Theory: –2D chip design Structures fab by focused-ion beam (FIB) treatment Pt electrodes by light lithography, physical vapor deposition, and subsequent lift-off Tomb Shwarmb et al, Nanoletter 2007, 3

3. March 3rd, 2008 EE235 Nanofabrication, University of California Berkeley 3D chip design Manufacturing process of 3-D chips: (I) first layer of Pt structures : photolithography, physical vapor deposition and lift off (II + III) layer of SiN evaporated on the first layer of Pt isolates both Pt layers (IV + V) definition of electrodes by cutting out trenches by FIB milling in two steps (V) final 3-D design and a SEM picture of 3-D chip. DEP manipulation parameters: f = 5MHz Yielding of the process dependent on -Chip design -Solution. SDS ( sodium dodecyl sulfate) reduce the bundled CNT attached on the electrode -Electrode material -Gap distance

4. March 3rd, 2008 EE235 Nanofabrication, University of California Berkeley Resistive Heating to achieve localized carbon nanotube synthesis  CMOS integration of nano structures (carbon nanotubes (CNTs))  Local and selective synthesis using silicon microstructures (MEMS)  Device applications to nano sensors and nano electronics 1.In-situ controlled growth of CNT 2.Assembly of single CNT 3.CNT/silicon contact discussed

5. March 3rd, 2008 EE235 Nanofabrication, University of California Berkeley Experimental Procedure Electric field assisted synthesis Gaps between Si structures Bias between Si (V 2 ) Electric field (V 2 / gaps) 5 ~ 10  m 2 ~ 5 V 0.2 ~ 1 V/  m Temperature C 2 H 2 /Ar gas Synthesis pressure 850 ~ 900  C 60 / 55 sccm 250 Torr Local synthesis of CNT

6. March 3rd, 2008 EE235 Nanofabrication, University of California Berkeley CNT-Silicon Heterojunction  CNT : Work function of CNT  Si : Electron affinity of silicon E g-Si : Band gap of silicon E i -E F : Fermi level for silicon  Bp : Barrier height  Bp = (  S + E g-Si ) -  CNT = 0.37~0.67 eV CNT: multiwall CNT (root and tip growth) Si: p + type, conc. 10 19 /cm 3 Contact resistance Specific contact resistivity  C : 10 -5 ~10 -4  -cm 2 [1]  Barrier height  Bp : 0.4 eV  Concentration of Silicon:10 19 /cm 3 (p-type) Contact area A : 2  10 -11 cm 2  Diameter of CNT : 50nm Contact resistance = 0.5 ~ 5M  [1] K. K. Ng and R. Liu, IEEE Trans. ED, 37, 1535 (1990)

7. March 3rd, 2008 EE235 Nanofabrication, University of California Berkeley Conclusion Top down approach: Photolithography and FIB, SOI standard process Bottom up: DEP manipulation (micro to nano scale) to CNT synthesis Localized heating: Better control of synthesis, higher yielding and capatibility for post-processing Contact Resistance Issue