1. Radiation detectors by post-processing CMOS a technologist's perspective Jurriaan Schmitz

2. Outline The semiconductor industry today The future, for industry and academia The concept of wafer post-processing Famous examples Recent successes Outlook

3. Cost per component Number of components in an IC 10 10 2 10 3 10 4 1 11010 2 10 3 10 4 10 5 Source: www.intel.com

4. Intel: Moore’s Law will outlive CMOS (Orczyk, Leuven, 2005)

5. Source: www.intel.com More performance…… at lower cost

6. IBM The state of the art (1): CMOS Nanometer precision Sub-ppm materials purity IBM Intel IBM

7. The state of the art (2): FLASH 50-nm FLASH Nanometer precision Sub-ppm materials purity

8. The state of the art (3): DRAM 58-nm DRAM technology Nanometer precision Sub-ppm materials purity SAMSUNG Qimonda (Infineon)

9. The Roadmap for Semiconductors The coming 10 years will bring: Faster, cheaper transistors Faster, cheaper memories Lower power, faster communication … again? Already, the worldwide production of transistors exceeds that of rice grains

10. Is Moore’s Law a blessing? It brought us into the Digital Age It makes the semiconductor business (somewhat) predictable for economists It creates a lot of employment … but there is little room for creativity! Transistors, transistors, transistors… Smaller, smaller, smaller…

11. But there is more! Source: ENIAC Industry Industry & academia Industry & academia

12. More than Moore: new functions Traditional IC: Computing Data Storage Electrical Communication Possible extensions: High quality passives Wireless communication Optical communication Sensing and Actuating How do we benefit from the present IC quality, and still add new functions? What’s 15*2.2? Thirty-three

13. The technological challenge How to combine electronics with sensors, actuators, optical components, …? Hybrid (solder components together) Pre-CMOS: Make component, then make CMOS on the same wafer Intermediate: Mix the component and CMOS processes … or post-CMOS: add components on top of a finished CMOS chip

14. MEMS-first monolithic integration Sandia 3-D accelerometer

15. Intermediate processing mix MEMS and CMOS fabrication NIST gas sensor Kovalgin, J. Electrochem. Soc. 153 (9) H181

16. Wafer post-processing a. Chip fabrication b. Wafer dicing

17. Wafer post-processing a. Chip fabrication b. Post-processing c. Wafer dicing

18. Logistics Chip fabrication: standard, at any regular (CMOS) fab Post-processing: special, in a custom CR laboratory Wafer dicing, packaging: specialized work like MEMS packaging, e.g. Amkor, Boschman a. Chip fabrication b. Post-processing c. Wafer dicing

19. Pros and cons We do not interfere with the (CMOS) fab process We can buy good quality chips We can use any lab for this We must keep the CMOS intact We have to think the final stages through very carefully! a. Chip fabrication b. Post-processing c. Wafer dicing Flexible for R&D; potential for mass-scale manufacturing

20. Example: Liquid-Crystal-on-Silicon Cover glass Electrode Liquid crystal Reflector CMOS

21. Example: Digital MicroMirror™

23. Example: CMOS image sensor R/G/B filter photodiode silicon R/G/B filter photodiode lens ~ 2  m Incident light Quartz cover Image sensing chip Chip housing

24. Samsung CMOS image sensor

25. CMOS on top of CMOS? B. Rajendran et al., IEEE Trans. El. Dev. 54 (4) 707. (3D integration) A. W. Topol et al., IBM J. Res. & Dev. 50 (4/5) 491 T ≤ 450 °C Technologically within reach! Issues: A cold dielectric A high quality semiconductor A killer application…

26. CMOS post-processing Careful treatment of the underlying CMOS: Temperature ≤ 400 °C Mild (or no) plasmas Maintain the H balance in the MOSFET Limited mechanical stress The CMOS properties must be unchanged: then the standard infrastructure can be used.

27. Low temperature ↔ high energy Cool the substrate, heat up the surface Laser annealingRemote-plasma CVD T. Shimoda et al., Nature 440, 783-786ICP source at MESA+ clean room

28. Beyond electronics: radiation imaging Cathode planes Particle Anode wires Traditional MWPCInGrid

29. InGrid: top performance! Excellent energy resolution for a gaseous detector 3-D track reconstruction Fast, low power, low cost per channel On-site data reduction / processing possible See contribution by V. M. Blanco Carballo

30. The next step: other imagers Light imagingIntegrate an MCP Semiconductor on a chip –3D integration –X-ray imaging –HEP tracking –…… Scintillator on imager chip CEA-LETI IEDM 2006 Vallerga UC Berkeley Wyrsch et al.: Si SigmaDigitalXray

31. Conclusions What can we build on top of CMOS? More electronics Light projectors CMOS imagers Radiation imaging detectors There’s plenty of room at the top!

32. Thanks… My low-temperature coworkers: Tom Aarnink, Victor Blanco Carballo, Arjen Boogaard, Ihor Brunets, Jisk Holleman, Alexey Kovalgin, Jiwu Lu, Joost Melai, Cora Salm, Sander Smits, Rob Wolters Max Chefdeville, Harry van der Graaf, Marten Bosma, Jan Visschers, Jan Timmermans Our sponsors: The Dutch Technology Foundation NXP Research Adixen/Alcatel ASM International Our website: http://sc.ewi.utwente.nl

33. Postprocessing: further reading Our website: http://sc.ewi.utwente.nl Jurriaan Schmitz, Nucl. Instr. Meth. A 576 (2007) 142.