1. Flip Flops, Registers Today: First Hour: Types of Latches, Flip Flips
Notes:
No Studios This week
About lab proto-boards and modules
Must stay in the lab
You are responsible for your assigned equipment for the entire semester.
Today:
First Hour: Types of Latches, Flip Flips
Section of Katz’s Textbook
In-class Activity #1
Second Hour: Storage and Shift Registers
Section 7.1 of Katz’s Textbook
In-class Activity #2

2. State Diagrams for Latches
Truth Table Summary
of R-S Latch Behavior
State Behavior of R-S Latch

3. State Diagram: R-S Latch
Theoretical R-S Latch State Diagram

4. Observed R-S Behavior
Very difficult to observe R-S Latch in the 1-1 state
Ambiguously returns to state 0-1 or 1-0
A so-called "race condition"

5. Making Other Latches Simplify by coupling inputs
NEXT STATE TABLE
J K Q Q+
HOLD
RESET
SET
TOGGLE
Simplify by coupling inputs
i.e., one input determines the other

6. Also called D flip-flop if edge-triggered
D Latch
NEXT STATE TABLE
Let J = D, K = D
J K Q Q+
HOLD
RESET
SET
TOGGLE
NEXT STATE TABLE
D Q Q+
RESET
0 1 0
SET
1 1 1 D
Also called D flip-flop if edge-triggered

7. Also called T flip-flop if edge-triggered
T Latch
NEXT STATE TABLE
Let J = T, K = T
J K Q Q+
HOLD
RESET
SET
TOGGLE
T Q Q+
HOLD
0 1 1
TOGGLE
1 1 0
NEXT STATE TABLE T
Also called T flip-flop if edge-triggered

8. Timing issues revisited
Latch Q K R Q Q J S Q
Set
Reset
Toggle
Problem: Keeps on toggling!

9. J-K Master/Slave F-F Latch J P K Clock Two-stage memory element R S Q
Master section - clock high
J-K inputs generate P outputs
Slave section - clock low
Ps are unchanging and generate Qs
Two-phase clock operation - Feedback has no effect until next time clock is high

10. Timing: master-slave Master Stage Slave Stage
Sample inputs while clock high
Sample inputs while clock low
Uses time to break feedback path from outputs to inputs!
Correct Toggle
Operation

11. Negative Edge-Triggered
Effect of Glitches
1's Catching problem:
If input = 1 any time during the clock period (even a glitch), it will be
interpreted as a 1 for computing output
 designer must use hazard-free logic
Solution: edge-triggered logic called “Flip-flops”
Built from 3 latches
Negative Edge-Triggered
D flipflop
When clock is high:
R=S=0 is the Hold state

12. Step-by-Step Analysis
Negative Edge-triggered D Flipflops
When clock goes high-to-low
R = D’, S = D
(new data D is latched)
Initially Clk = 1
R = S = 0
(Hold)

13. Step-by-Step Analysis
Negative Edge-triggered D Flipflops
When clock goes high-to-low
R = D’, S = D
(new data D is latched)
If clock remains low, and
D changes,
(Previous value of D is held)

14. Latches vs Flip-Flops Input/Output Behavior of Latches and Flipflops
Type When Inputs are Sampled When Outputs are Valid
Un-clocked always propagation delay from
latch input change
level clock high propagation delay from
-sensitive (Tsu, Th around input change
latch falling clock edge)
positive edge clock lo-to-hi transition propagation delay from
flipflop (Tsu, Th around rising edge of clock
rising clock edge)
negative edge clock hi-to-lo transition propagation delay from
flipflop (Tsu, Th around falling edge of clock
falling clock edge)
master/slave clock hi-to-lo transition propagation delay from
flipflop (Tsu, Th around falling edge of clock

15. Comparison of FFs R-S Clocked Latch:
used as storage element in narrow width clocked systems
its use is not recommended!
however, fundamental building block for other flipflop types
J-K Flipflop:
versatile building block
can be used to implement D and T FFs
usually requires least amount of logic to implement ƒ(in,Q,Q+)
but has two inputs with increased wiring complexity
because of 1's catching, never use master/slave J-K FFs
edge-triggered varieties exist
D Flipflop:
minimizes wires, much preferred in VLSI technologies
simplest design technique
best choice for storage registers
T Flipflops:
don't really exist, constructed from J-K FFs
usually best choice for implementing counters
Preset and Clear inputs highly desirable!!

16. Behavior the same unless input changes
TTL schematics
7474
Edge triggered device sample inputs on the event
edge
Transparent latches sample inputs as long as the
clock is asserted
Timing Diagram:
7476 D
Clk Q
7474
Bubble here
for negative
edge triggered
device Q
7476
Behavior the same unless input changes
while the clock is high

17. TYPO!!: For Part (a) start with circle (0, 1)
Do Activity #1 Now
TYPO!!: For Part (a) start with circle (0, 1)
J-K NEXT STATE TABLE
J K Q Q+
HOLD
RESET
SET
TOGGLE D D
Holds D when
clock goes low D’ R Q
Clk Q S D
Holds D when
clock goes low D D
Pages of Katz

18. Sequential Logic Components
Flipflops: most primitive "packaged" sequential circuits
More complex sequential building blocks:
Storage registers, Shift registers, Counters
Available as components in the TTL Catalog
Registers
Store a word (4 to 64 bits)
E.g.: Pentium has several registers
Counters
Count thru a sequence of states
E.g., the seconds display on a clock.
Both of these have many variations.

19. Storage Registers Storage registers store data, without changing it.
A D F/F is a 1-bit storage register.
A Register File stores a group of words of data.
You specify which word to read or write.
A Random-Access Memory is like a large register file. It may store 32MB of data or more.

20. Multi-bit Storage Registers
use D F/Fs in groups to make a multibit register
Clocks in 4 bits in parallel, or resets to 0.

21. 74171 Quadruple D F/F with Clear
Triangle indicates clock input
No bubble indicates positive edge triggered
The /CLR clears all 4 bits
This stores 4 bits in parallel

22. Register Variants Sometimes there’s also a LOAD input.
When LOAD is false, the F/F doesn’t change.
When LOAD is true during the clock edge, the F/F updates itself.
Sometimes the outputs are 3-state or open collector.
This allows several registers to be connected to the same output wire

23. 74377 Octal D F/Fs with Enable
Positive edge triggered
... but only when /EN is active LO
Stores an 8 bit number

24. 74374 Octal D F/Fs with 3-State Outputs
Positive edge triggered
Stores an 8 bit number
/OE is active LO output enable
Determines when register contents are visible at the outputs
Note: LW uses different labels from the 377, and from Katz!

25. Register Files Store several words
You read or write one word at a time.
by-4 Register File with 3-State Outputs
4 words of 4 bits each
Data in: D1,D2,D3,D4 Data out: Q1,Q2,Q3,Q4
Read selects: RB,RA Write selects: WB,WA
Active low read enable /GR, write enable /GW
Can read and write simultaneously.
No clock. Read or write when enables asserted.
Watch out for glitches!
To write Word 1, set GW = 0 and (WB, WA) to (0,1)
To read Word 2, set GR = 0 and (RB, RA) to (1,0)

26. Random Access Memories
Same idea as a register file, but optimized for very many words.
Small RAM: bit words.
Larger RAM: 4 million 8-bit words.
More details later.

27. Shift Registers
Some registers are designed to change their stored data.
Shift registers shift their bits left or right.
For example, right shift:
Original contents 1000
Shift right:
Shift again:
…and again:
… once more, wrapping: 1000
Application: send a word to a modem bit-by-bit.
We need some way to initialize the shift register.

28. Input and Output Serial input
The shift register doesn’t wrap around from right to left.
Instead, the user provides the new leftmost bit.
Parallel input
You can specify the whole word at once.
Serial output
The bit just shifted off the right is visible at a pin.
Parallel output
Every stored bit is visible at an output pin.
This uses more pins, which can be a problem.

29. 74194 -more- 4 bit bidirectional universal shift register
4 modes set by S1,S0
00: hold data (QA,QB,QC,QD)
01: shift right (SR,QA,QB,QC)
10: shift left (QB,QC,QD,SL)
11: parallel load
SL (aka LSI): left shift input
SR (aka RSI): right shift input
Positive edge triggered
/CLR: asynchronous clear

30. 74194 continued Notation conflicts:
LogicWorks uses SL, SR. Katz uses LSI, RSI.
LW uses A,B,C,D for inputs and QA,QB,QC,QD for outputs.
Motorola uses P0,P1,P2,P3 for inputs, Q0,Q1,Q2,Q3 for outputs and DSR & DSL for serial inputs.
Note that the normal LW convention is that A is the lo-order bit. This is the way you normally connect the hex keyboard and the hex display. For the 194, A and QA are the hi-order bits. It's confusing.
Right shift in more detail. All together on the rising clock:
SR  QA, QA  QB, QB  QC, QC  QD, QD is lost.
Connecting QD to SR makes a circular shift register.
Left shift in more detail.
SL  QD, QD  QC, QC  QB, QB  QA, QA is lost.

31. Do Activity #2 Now For Next Class:
TYPO: Question b, part 2, WB, WA = 11
Due: End of Class Today
RETAIN THE LAST PAGES (#3 & #4)!!
For Next Class:
Bring Randy Katz Textbook, & TTL Data Book
Required Reading:
Sec 7.2, 7.3 of Katz
This reading is necessary for getting points in the Studio Activity!