1. 1 ASIC 120: Digital Systems and Standard-Cell ASIC Design Tutorial 2: Introduction to VHDL February 1, 2006

2. 2 Outline State Machines HDL design flow Format of a VHDL file Combinational statements –assignments, conditionals, when … else Sequential statements –processes, if … then … else

3. 3 Summary of Previous Tutorial Digital Systems Combinational Logic –NOT, AND, OR, XOR, NAND, etc. –mux, half-adder, full-adder Sequential Logic –flip-flop/register, shift register, counter

4. 4 Recall: Sequential Circuits Sequential –computation involves a feedback loop (memory) Example: ring counter Clk DFF D Q S C Init DFF D Q S C DFF D Q S C DFF D Q S C

5. 5 State Machines We actually mean a Finite State Machine (FSM) –models behaviour Components relevant to digital design –states –transitions –inputs –outputs

6. 6 State Machines Represented as a state diagram S0S0 S1S1 S3S3 1/0 S2S2 0/0 1/1 0/1 1/1 1/0 0/1 0/0 State Transition Output Input

7. 7 State Machines Or as a state table Present State Input A Next State Output X S0S0 0 S0S0 0 S0S0 1 S1S1 0 S1S1 0 S3S3 1 S1S1 1 S2S2 1 S2S2 0 S3S3 1 S2S2 1 S2S2 1 S3S3 0 S1S1 0 S3S3 1 S0S0 0 Input A Output X S0S0 S1S1 S3S3 1/0 S2S2 0/0 1/1 0/1 1/1 1/0 0/1 0/0

8. 8 State Machines Encode states into binary Present State Input A Next State Output X 000 0 1010 0111 011101 0111 101 1 110010 111000 Input A Output X 00 01 11 1/0 10 0/0 1/1 0/1 1/1 1/0 0/1 0/0

9. 9 State Machines Some things to note –we assigned S 0 = 00, S 1 = 01, etc., but state/bit mapping can be completely arbitrary –output is occurring on the transitions, this is called a Mealy state machine –where the output is dependent only on the current state, it is called a Moore machine

10. 10 State Machines Remodelled as a Moore state machine Present State Input A Next State Output X 000 0 1010 0111 011101 0111 101 1 110010 111000 Input A Output X 00 (0) 01 (0) 11 (1) 1 10 (1) 0 1 1 0 0

11. 11 State Machines This example is rather contrived –only dealing with abstract “states”, but imagine application to automatic door, traffic lights, etc. –Moore and Mealy machine looked the same but they won’t always

12. 12 State Machines 00 (0) 01 (0) 11 (1) 1 10 (1) 0 1 1 0 0 00 01 11 1/0 10 0/0 1/1 0/1 1/1 1/0 0/1 0/0 Moore Mealy

13. 13 State Machines: Moore vs. Mealy Mealy can often be represented using less states –transitions can produce different output Even with more states, Moore often creates less hardware –less combinational logic –on an FPGA, registers (D flip-flops) are “free”

14. 14 State Machines in Digital Hardware This state machine requires two registers (D flip-flops), since there are four states Basic procedure: 1)create state table 2)derive FF input equations (and output equations) from next state column with respect to present state and inputs 3)simplify equations 4)draw hardware

15. 15 State Machines in Digital Hardware Let the two state bits (registers) be G and H –we also have input A G = GHA + GHA + GHA + GHA H = GHA + GHA + GHA + GHA X = G  H Present State A Next State X GHGH 000000 001010 010111 011101 100111 101101 110010 111000

16. 16 State Machines in Digital Hardware Simplify the equations G = G  H H = GHA + A X = G  H Present State A Next State X GHGH 000000 001010 010111 011101 100111 101101 110010 111000

17. 17 State Machines in Digital Hardware Draw the hardware G = G  H H = GHA + A X = G  H DFF D Q DFF D Q GH A A X Clk

18. 18 State Machines in Digital Hardware I’ve skipped many details and nuances –see ECE 223 course notes State machines can get very complicated –often don’t work out states in this detail –let synthesis tools do it

19. 19 Optimization of State Machines Outside the scope of this tutorial Summary –reduce number of states by combining states, while preserving equivalent functionality –bit encoding can affect the size of the circuitry generated to implement it

20. 20 Ring Counter Is this a state machine? Yes: every sequential circuit is a state machine Clk DFF D Q S C Init DFF D Q S C DFF D Q S C DFF D Q S C

21. 21 Back to Register Transfer Level (RTL) Logic Register Clock Cloud of Logic Register Cloud of Logic Data In Data Out Feedback Combinational Sequential

22. 22 Hardware Description Languages (HDLs) HDLs describes in text a digital circuit Examples –VHDL (we will look at this next time) –Verilog –AHDL –JHDL

23. 23 Hardware Description Languages (HDLs) schematics are useful for… –drawing high level diagrams –manually working out simple pieces of logic HDLs are useful for… –describing complex digital systems HDLs are not... –software programming languages (C, Java, assembly, etc.)

24. 24 Think Digital When designing a digital system in VHDL, it is important to remember the relation between code constructs and actual hardware

25. 25 HDL Design Flow 1.Concept, requirements analysis 2.High level design 3.Functional implementation (need not be synthesizable) 4.Functional simulation (3 -> 4 until functionality is good) 5.Synthesizable implementation 6.Synthesizable simulation (6 -> 5 until functionality is good) 7.Timing simulation (7 -> 5 until timing is good; this step I often bypassed in practice) 8.Synthesis design is compiled to hardware we will cover this in more detail later 8 -> 5 if design doesn’t compile or doesn’t fit 9.Testing in hardware (9 -> 5 if something is wrong)

26. 26 What does “synthesizable” mean? Synthesizable means that a given design can be compiled into hardware –FPGA (reprogrammable ASIC) –ASIC A non-synthesizable design can be simulated in software and is useful for –working out functionality –testing out concepts –test benches (covered in detail later)

27. 27 Levels of Abstraction Behavioural Dataflow Structural

28. 28 Components of a VHDL File library –ieee, etc. use entity –defines the interface architecture –defines the functionality component –reusable functionality multiple entity/architectures in one file

29. 29 Why do we use IEEE libraries? standard VHDL libraries are limited to two values: 0 and 1 this is fine for theory, but in practice a physical wire can have other values more on this in later tutorials

30. 30 Inputs and Outputs declared in the entity the “pins” of the hardware block can only be input, output, or I/O output pins cannot be read from –for example, if I assign a value to an output pin I cannot “read” that value back in another place –output pins are like black holes in this way

31. 31 Signals Signals are the internal “wires” of your design Can be assigned a value, or have their value read Signals can be read in multiple places, but assigned in only one place –“cannot have multiple output pins driving a wire”

32. 32 Buses Provide an easy way to group multiple signals or ports

33. 33 Combinational Logic In VHDL: “Concurrent Statements” Remember: all functionality is defined within architecture block Order doesn’t matter Types of concurrent statements –assignments –conditional assignments –processes

34. 34 Combinational Assignments destination <= source_logic; examples: X <= A AND B; Y <= NOT (A AND B); Z <= A XOR B AND C NOT B;

35. 35 Conditional Assignments destination<=source_logic_1 when condition_1 else source_logic_2 when condition_2 else source_logic_3; example: X<= A AND B when Sel = “00” else NOT (A AND B) when Sel = “01” else A XOR B when Sel(0) & Sel(1) = “10”

36. 36 Conditional Assignment: A MUX Conditional assignments are modelled physically as a multiplexer 00 01 10 11 X<=A AND B when Sel = “00” else NOT (A AND B) when Sel = “01” else A XOR B when Sel(0) & Sel(1) = “10” Sel(0) Sel(1) Sel ABAB ABAB X

37. 37 Brackets and The & Operator Brackets –used to reference parts of buses & Operator –signal concatenation operator –used for constructing buses out of single wire signals, or parts of other buses

38. 38 Processes Contain chunks of VHDL code Can be purely combinational Most useful for sequential logic –controlled by a clock processes are executed in parallel, in any order Processes can optionally be named

39. 39 Process Statement [process_name:] process (sensitivity_list) declarations begin sequential_statements end process;

40. 40 Sequential Logic In VHDL: “Sequential Statements” Within a process, statements execute sequentially –important to remember that logic is tied back to underlying hardware

41. 41 If … Then …Else Statement Like the concurrent “when … else” statement, modelled as a multiplexer if first_condition then statements elsif second_condition then statements else statements end if;

42. 42 MUX with an If Statement process(Sel, A, B, C, D) begin if Sel = "00" then Y <= A; elsif Sel = "01" then Y <= B; elsif Sel = "10" then Y <= C; elsif Sel = "11" then Y <= D; end if; end process;

43. 43 MUX with an If Statement Note that this mux is a combinational mux –i.e., not governed by a clock A B C D 00 01 10 11 Sel(0) Sel(1) Y

44. 44 Clocked Processes Or: “Sequential Processes” Consider a “clocked mux”: process begin wait until rising_edge(Clk); if Sel = "00" then Y <= A; elsif Sel = "01" then Y <= B; elsif Sel = "10" then Y <= C; elsif then Y <= D; end if; end process;

45. 45 Clocked Processes Or: “Sequential Processes” Consider a “clocked mux”: process begin wait until rising_edge(Clk); if Sel = "00" then Y <= A; elsif Sel = "01" then Y <= B; elsif Sel = "10" then Y <= C; elsif then Y <= D; end if; end process; A B C D 00 01 10 11 Sel(0) Sel(1) Y DFF D Q Clk

46. 46 Clocked Processes Statements are essentially executed in series Important to always keep in mind underlying hardware

47. 47 Clocked Processes Consider: process begin wait until rising_edge(Clk); if Sel = ‘0’ then Y <= A; else Y <= B; end if; if Sel = ‘0’ then Z <= B; else Z <= A; end if; end process;

48. 48 Clocked Processes Consider: process begin wait until rising_edge(Clk); if Sel = ‘0’ then Y <= A; else Y <= B; end if; if Sel = ‘0’ then Z <= B; else Z <= A; end if; end process; A B 0 1 Sel Y DFF D Q Clk B A 0 1 Sel Z DFF D Q Clk

49. 49 Clocked Processes This code produces the same hardware: process begin wait until rising_edge(Clk); if Sel = ‘0’ then Y <= A; Z <= B; else Y <= B; Z <= A; end if; end process; A B 0 1 Sel Y DFF D Q Clk B A 0 1 Sel Z DFF D Q Clk

50. 50 Remember Always consider the underlying hardware! –ask yourself: what does the VHDL code I’m writing actually represent?

51. 51 Preview of Next Tutorial Intermediate VHDL –sequential statements continued more on registers, case, loops –latch inference –loops –other signal values besides ‘0’ and ‘1’ –more VHDL data types –attributes, type definitions

52. 52 Summary State Machines HDL design flow Format of a VHDL file Combinational statements –assignments, conditionals, when … else Sequential statements –processes, if … then … else

53. 53 UW ASIC Design Team www.asic.uwaterloo.ca reference material –Prof. Hamel’s Winter 2005 ECE 223 course notes http://www.ece.uwaterloo.ca/~ece223/jhamel/ –Accolade VHDL reference (excellent!): http://www.acc-eda.com/vhdlref/ –Bryce Leung’s tutorials (UW ASIC website) –Mike Goldsmith’s tutorials (UW ASIC website) –your course notes my contact info: Jeff Wentworth, j.wentworth@gmail.com