1. Survey of Reconfigurable Logic Technologies
ECE 448
Lecture 11
Survey of Reconfigurable Logic Technologies
ECE 448 – FPGA and ASIC Design with VHDL

2. Resources Xcell Journal available for FREE on line
or in the printed
FPGA and Structured ASIC Journal
available for FREE by or on the
ECE 448 – FPGA and ASIC Design with VHDL

3. Technology Timeline ECE 448 – FPGA and ASIC Design with VHDL
The Design Warrior’s Guide to FPGAs Devices, Tools, and Flows. ISBN Copyright © 2004 Mentor Graphics Corp. (
ECE 448 – FPGA and ASIC Design with VHDL

4. Programmable Logic Devices
ECE 448 – FPGA and ASIC Design with VHDL

5. First Programmable Logic Devices
The Design Warrior’s Guide to FPGAs Devices, Tools, and Flows. ISBN Copyright © 2004 Mentor Graphics Corp. (
ECE 448 – FPGA and ASIC Design with VHDL

6. Programmable logic device as a black box
Logic gates
and
programmable
switches
Inputs
(logic variables)
Outputs
(logic functions)
ECE 448 – FPGA and ASIC Design with VHDL

7. General structure of a PLA (Programmable Logic Array)x x x 1 2 n
Input buffers
& inverters x x x x 1 1 n n P 1
AND plane
OR plane P k f f 1 m
ECE 448 – FPGA and ASIC Design with VHDL

8. Gate-level diagram of a PLAx x x 1 2 3
Programmable
connections
OR plane P 1 P 2 P 3 P 4
AND plane f 1 f 2
ECE 448 – FPGA and ASIC Design with VHDL

9. Customary schematic for a PLA1 P 2 x 3
OR plane
AND plane 4
ECE 448 – FPGA and ASIC Design with VHDL

10. Programmable Array Logicf 1 P 2 x 3
AND plane 4
ECE 448 – FPGA and ASIC Design with VHDL

11. Macrocell at the output of PAL1
To AND plane D Q
Clock
Select
Enable
Flip-flop
ECE 448 – FPGA and ASIC Design with VHDL

12. A generic structure of CPLD (Complex Programmable Logic Device)
The Design Warrior’s Guide to FPGAs Devices, Tools, and Flows. ISBN Copyright © 2004 Mentor Graphics Corp. (
ECE 448 – FPGA and ASIC Design with VHDL

13. Structure of a CPLD Interconnection wires I/O block PAL-like block
ECE 448 – FPGA and ASIC Design with VHDL

14. A section of a CPLD ECE 448 – FPGA and ASIC Design with VHDL D Q
PAL-like block
ECE 448 – FPGA and ASIC Design with VHDL

15. Connections between the programmable interconnect matrix and simple PAL-like blocks
The Design Warrior’s Guide to FPGAs Devices, Tools, and Flows. ISBN Copyright © 2004 Mentor Graphics Corp. (
ECE 448 – FPGA and ASIC Design with VHDL

16. Field Programmable Gate Arrays
ECE 448 – FPGA and ASIC Design with VHDL

17. General structure of an FPGA
The Design Warrior’s Guide to FPGAs Devices, Tools, and Flows. ISBN Copyright © 2004 Mentor Graphics Corp. (
ECE 448 – FPGA and ASIC Design with VHDL

18. Xilinx CLB ECE 448 – FPGA and ASIC Design with VHDL
The Design Warrior’s Guide to FPGAs Devices, Tools, and Flows. ISBN Copyright © 2004 Mentor Graphics Corp. (
ECE 448 – FPGA and ASIC Design with VHDL

19. Simplified view of a Xilinx Logic Cell
The Design Warrior’s Guide to FPGAs Devices, Tools, and Flows. ISBN Copyright © 2004 Mentor Graphics Corp. (
ECE 448 – FPGA and ASIC Design with VHDL

20. RAM Blocks and Multipliers in Xilinx FPGAs
The Design Warrior’s Guide to FPGAs Devices, Tools, and Flows. ISBN Copyright © 2004 Mentor Graphics Corp. (
ECE 448 – FPGA and ASIC Design with VHDL

21. Embedded Microprocessor Cores
The Design Warrior’s Guide to FPGAs Devices, Tools, and Flows. ISBN Copyright © 2004 Mentor Graphics Corp. (
ECE 448 – FPGA and ASIC Design with VHDL

22. Virtex-II Pro Architecture2 4 6 1 5 3
Features:
Processor Block
RocketIO Multi-Gigabit Transceivers
CLB and Configurable Logic
SelectIO-Ultra
Digital Clock Managers
Multipliers and Block SelectRAM
ECE 448 – FPGA and ASIC Design with VHDL

23. ECE 448 – FPGA and ASIC Design with VHDL

24. Processor Block Contains four components:
Embedded IBM PowerPC 405-D5 RISC CPU core
On-Chip Memory (OCM) controllers and interface
Clock/control interface logic
CPU-FPGA Interfaces
IBM CoreConnect Bus Architecture Features:
Processor Local Bus (PLB)
On-chip Peripheral Bus (OPB)
Device Control Register (DCR) Bus
BRAM
BRAM
Control
OCM Controller
PPC 405
Core
FPGA CLB Array
OCM Controller
Interface Logic
BRAM
BRAM
ECE 448 – FPGA and ASIC Design with VHDL

25. PowerPC Cores ECE 448 – FPGA and ASIC Design with VHDL PowerPC System

26. Embedded Development Kit (EDK)
Hardware Flow
Software Flow
Processor IP,
Microprocessor Peripheral Description Files
VHDL / Verilog
C / C++ Code
Libraries
PlatGen
Synthesizer
Compiler
LibGen
Microprocessor Hardware Specification File
Microprocessor Software Specification File
EDIF IP Netlists
Object Files
ISE / Xflow
System Constraint File
Linker
Bitstream
Data2MEM
Executable
Download to FPGA
ECE 448 – FPGA and ASIC Design with VHDL

27. A simple clock tree ECE 448 – FPGA and ASIC Design with VHDL
The Design Warrior’s Guide to FPGAs Devices, Tools, and Flows. ISBN Copyright © 2004 Mentor Graphics Corp. (
ECE 448 – FPGA and ASIC Design with VHDL

28. Clock Manager ECE 448 – FPGA and ASIC Design with VHDL
The Design Warrior’s Guide to FPGAs Devices, Tools, and Flows. ISBN Copyright © 2004 Mentor Graphics Corp. (
ECE 448 – FPGA and ASIC Design with VHDL

29. Jitter ECE 448 – FPGA and ASIC Design with VHDL
The Design Warrior’s Guide to FPGAs Devices, Tools, and Flows. ISBN Copyright © 2004 Mentor Graphics Corp. (
ECE 448 – FPGA and ASIC Design with VHDL

30. Removing Jitter ECE 448 – FPGA and ASIC Design with VHDL
The Design Warrior’s Guide to FPGAs Devices, Tools, and Flows. ISBN Copyright © 2004 Mentor Graphics Corp. (
ECE 448 – FPGA and ASIC Design with VHDL

31. Frequency Synthesis ECE 448 – FPGA and ASIC Design with VHDL
The Design Warrior’s Guide to FPGAs Devices, Tools, and Flows. ISBN Copyright © 2004 Mentor Graphics Corp. (
ECE 448 – FPGA and ASIC Design with VHDL

32. Phase shifting Figure 4-20 ECE 448 – FPGA and ASIC Design with VHDL
The Design Warrior’s Guide to FPGAs Devices, Tools, and Flows. ISBN Copyright © 2004 Mentor Graphics Corp. (
Figure 4-20
ECE 448 – FPGA and ASIC Design with VHDL

33. Removing Clock Skew ECE 448 – FPGA and ASIC Design with VHDL
The Design Warrior’s Guide to FPGAs Devices, Tools, and Flows. ISBN Copyright © 2004 Mentor Graphics Corp. (
ECE 448 – FPGA and ASIC Design with VHDL

34. General-Purpose IO Blocks
The Design Warrior’s Guide to FPGAs Devices, Tools, and Flows. ISBN Copyright © 2004 Mentor Graphics Corp. (
ECE 448 – FPGA and ASIC Design with VHDL

35. Using High-Speed Tranceivers to Communicate Between Devices
The Design Warrior’s Guide to FPGAs Devices, Tools, and Flows. ISBN Copyright © 2004 Mentor Graphics Corp. (
ECE 448 – FPGA and ASIC Design with VHDL

36. Programming Reconfigurable
Logic Devices
ECE 448 – FPGA and ASIC Design with VHDL

37. A Fusible Link Technologies: Unprogrammed Device
The Design Warrior’s Guide to FPGAs Devices, Tools, and Flows. ISBN Copyright © 2004 Mentor Graphics Corp. (
ECE 448 – FPGA and ASIC Design with VHDL

38. A Fusible Link Technologies: Programmed Device
The Design Warrior’s Guide to FPGAs Devices, Tools, and Flows. ISBN Copyright © 2004 Mentor Graphics Corp. (
ECE 448 – FPGA and ASIC Design with VHDL

39. An Antifuse Technology: Unprogrammed Device
The Design Warrior’s Guide to FPGAs Devices, Tools, and Flows. ISBN Copyright © 2004 Mentor Graphics Corp. (
ECE 448 – FPGA and ASIC Design with VHDL

40. An Antifuse Technology: Programmed Device
The Design Warrior’s Guide to FPGAs Devices, Tools, and Flows. ISBN Copyright © 2004 Mentor Graphics Corp. (
ECE 448 – FPGA and ASIC Design with VHDL

41. Growing an Antifuse ECE 448 – FPGA and ASIC Design with VHDL
The Design Warrior’s Guide to FPGAs Devices, Tools, and Flows. ISBN Copyright © 2004 Mentor Graphics Corp. (
ECE 448 – FPGA and ASIC Design with VHDL

42. EPROM Technology ECE 448 – FPGA and ASIC Design with VHDL
The Design Warrior’s Guide to FPGAs Devices, Tools, and Flows. ISBN Copyright © 2004 Mentor Graphics Corp. (
ECE 448 – FPGA and ASIC Design with VHDL

43. An EPROM Transistor-Based Memory Cell
The Design Warrior’s Guide to FPGAs Devices, Tools, and Flows. ISBN Copyright © 2004 Mentor Graphics Corp. (
ECE 448 – FPGA and ASIC Design with VHDL

44. EEPROM Technology ECE 448 – FPGA and ASIC Design with VHDL
The Design Warrior’s Guide to FPGAs Devices, Tools, and Flows. ISBN Copyright © 2004 Mentor Graphics Corp. (
ECE 448 – FPGA and ASIC Design with VHDL

45. Static RAM-based Technology
The Design Warrior’s Guide to FPGAs Devices, Tools, and Flows. ISBN Copyright © 2004 Mentor Graphics Corp. (
ECE 448 – FPGA and ASIC Design with VHDL

46. Summary of Programming Technologies
The Design Warrior’s Guide to FPGAs Devices, Tools, and Flows. ISBN Copyright © 2004 Mentor Graphics Corp. (
ECE 448 – FPGA and ASIC Design with VHDL

47. ECE 448 – FPGA and ASIC Design with VHDL
The Design Warrior’s Guide to FPGAs Devices, Tools, and Flows. ISBN Copyright © 2004 Mentor Graphics Corp. (
ECE 448 – FPGA and ASIC Design with VHDL

48. SRAM FPGA Configuration
Loading the bitstream into internal memory by delivering it through one of the configuration interfaces
Configuration phases:
Clearing the configuration memory
Initialization
Bitstream loading
Device startup
JTAG
SelectMAP
Slave/Master Serial
ICAP
Correspond to configuration modes
Configuration Device
SRAM FPGA
Bitstream
Configuration
Interface
A series of command and data
Configuration
Logic
Configuration
Memory
ECE 448 – FPGA and ASIC Design with VHDL

49. Configuration of SRAM based FPGAs
The Design Warrior’s Guide to FPGAs Devices, Tools, and Flows. ISBN Copyright © 2004 Mentor Graphics Corp. (
ECE 448 – FPGA and ASIC Design with VHDL

50. FPGA Configuration Modes
The Design Warrior’s Guide to FPGAs Devices, Tools, and Flows. ISBN Copyright © 2004 Mentor Graphics Corp. (
ECE 448 – FPGA and ASIC Design with VHDL

51. Serial Load with FPGA as a Master
The Design Warrior’s Guide to FPGAs Devices, Tools, and Flows. ISBN Copyright © 2004 Mentor Graphics Corp. (
ECE 448 – FPGA and ASIC Design with VHDL

52. Daisy-Chaining FPGAs ECE 448 – FPGA and ASIC Design with VHDL
The Design Warrior’s Guide to FPGAs Devices, Tools, and Flows. ISBN Copyright © 2004 Mentor Graphics Corp. (
ECE 448 – FPGA and ASIC Design with VHDL

53. Parallel Load with FPGA as a Master (off-the-shelf memory)
The Design Warrior’s Guide to FPGAs Devices, Tools, and Flows. ISBN Copyright © 2004 Mentor Graphics Corp. (
ECE 448 – FPGA and ASIC Design with VHDL

54. Parallel Load with FPGA as a Master (special-purpose memory)
The Design Warrior’s Guide to FPGAs Devices, Tools, and Flows. ISBN Copyright © 2004 Mentor Graphics Corp. (
ECE 448 – FPGA and ASIC Design with VHDL

55. Parallel Load with FPGA as a Slave
The Design Warrior’s Guide to FPGAs Devices, Tools, and Flows. ISBN Copyright © 2004 Mentor Graphics Corp. (
ECE 448 – FPGA and ASIC Design with VHDL

56. Using the JTEG Port JTEG = Joint Test Action Group, IEEE 1149.1
The Design Warrior’s Guide to FPGAs Devices, Tools, and Flows. ISBN Copyright © 2004 Mentor Graphics Corp. (
ECE 448 – FPGA and ASIC Design with VHDL

57. Internal Processor Boundary Scan Chain
The Design Warrior’s Guide to FPGAs Devices, Tools, and Flows. ISBN Copyright © 2004 Mentor Graphics Corp. (
ECE 448 – FPGA and ASIC Design with VHDL

58. Reconfiguration Interfaces in Xilinx FPGAs
Internal Port
ICAP
(Virtex-II)
JTAG
SelectMap (8 bits Parallel)
ECE 448 – FPGA and ASIC Design with VHDL

59. Configuration times of selected FPGA devices
ECE 448 – FPGA and ASIC Design with VHDL